Altera Stratix V Avalon-MM Interface for PCIe Solutions Instrukcja Użytkownika Strona 80
- Strona / 184
- Spis treści
- BOOKMARKI
Oceniono. / 5. Na podstawie oceny klientów
Table 5-7: CvP Status
The CvP Status register allows software to monitor the CvP status signals.
Bits Register Description Reset Value Access
[31:26] Reserved 0x00 RO
[25] PLD_CORE_READY. From FPGA fabric. This status bit is
provided for debug.
Variable RO
[24] PLD_CLK_IN_USE. From clock switch module to fabric. This
status bit is provided for debug.
Variable RO
[23] CVP_CONFIG_DONE. Indicates that the FPGA control block has
completed the device configuration via CvP and there were
no errors.
Variable RO
[22] Reserved Variable RO
[21] USERMODE. Indicates if the configurable FPGA fabric is in user
mode.
Variable RO
[20] CVP_EN. Indicates if the FPGA control block has enabled CvP
mode.
Variable RO
[19] CVP_CONFIG_ERROR. Reflects the value of this signal from the
FPGA control block, checked by software to determine if
there was an error during configuration.
Variable RO
[18] CVP_CONFIG_READY. Reflects the value of this signal from the
FPGA control block, checked by software during
programming algorithm.
Variable RO
[17:0] Reserved Variable RO
Table 5-8: CvP Mode Control
The CvP Mode Control register provides global control of the CvP operation.
Bits Register Description Reset Value Access
[31:16] Reserved. 0x0000 RO
[15:8] CVP_NUMCLKS.
This is the number of clocks to send for every CvP data write. Set
this field to one of the values below depending on your configura‐
tion image:
• 0x01 for uncompressed and unencrypted images
• 0x04 for uncompressed and encrypted images
• 0x08 for all compressed images
0x00 RW
[7:3] Reserved. 0x0 RO
[2] CVP_FULLCONFIG. Request that the FPGA control block
reconfigure the entire FPGA including the Stratix V Hard IP for
PCI Express, bring the PCIe link down.
1’b0 RW
UG-01097_avmm
2014.12.15
CvP Registers
5-11
Registers
Altera Corporation
Send Feedback
- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Altera FPGA 8
- Debug Features 10
- IP Core Verification 10
- Recommended Speed Grades 11
- Running Qsys 14
- Generating the Example Design 15
- Simulating Altera Designs 17
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 19
- Programming a Device 20
- Parameter Settings 21
- Parameter Value Description 22
- Device Capabilities 25
- Error Reporting 26
- Link Capabilities 27
- MSI and MSI-X Capabilities 28
- Power Management 29
- Clock Domains on page 6-5 33
- Application Layer 34
- RX Avalon-MM Master Signals 36
- Clock Signals 41
- Signal Direction Description 42
- Variant Logical Interfaces 49
- Hard IP Status Extension 50
- Field and Bit Map 58
- 0134678951 58
- Bit(s) Field Description 59
- Serial Data Signals 60
- PIPE Interface Signals 64
- Test Signals 69
- Registers 70
- Altera-Defined VSEC Registers 78
- CvP Registers 79
- Address Range Register 83
- Bit Name Access Description 84
- Bits Name Access Description 85
- PCI Express Mailbox Registers 86
- Avalon-MM Mailbox Registers 90
- Address Name Access 91
- Description 91
- Byte Offset 91
- Register Dir Description 91
- Sending a Write TLP 97
- Root Port TLP Data Registers 99
- UG-01097_avmm 100
- 2014.12.15 100
- Related Information 101
- Bits Register Description 102
- Reset and Clocks 105
- Hard IP for PCI Express 106
- Example Design 106
- Clock Domains 109
- Data Rate Frequency 110
- Clock Summary 112
- Interrupts for Endpoints 113
- MSI/MSI‑X Support 115
- MsiIntfc_o[81:0] 116
- MsiControl_o[15:0] 116
- MsixIntfc_o[15:0] 116
- IntxReq_i 116
- IntxAck_o 116
- Error Handling 117
- Physical Layer Errors 118
- Data Link Layer Errors 118
- Transaction Layer Errors 119
- Error Type Description 120
- Status Bit Conditions 123
- IP Core Architecture 125
- Hard IP for PCI Express 126
- Top-Level Interfaces 127
- Avalon-MM Interface 127
- Clocks and Reset 127
- Transceiver Reconfiguration 127
- Interrupts 127
- Data Link Layer 128
- Altera Corporation 129
- Send Feedback 129
- Physical Layer 130
- TX Packets 131
- Avalon‑MM Bridge TLPs 135
- Byte Enable Value Description 136
- PCI Express Avalon-MM Bridge 138
- RX Block 144
- Avalon-MM RX Master Block 144
- TX Block 145
- Interrupt Handler Block 145
- Enable PLL calibration 147
- Throughput Optimization 151
- Throughput of Posted Writes 153
- Design Implementation 155
- CONF_DONE 156
- Endpoint Reset 156
- Root Port Reset 156
- SDC Timing Constraints 157
- Optional Features 159
- ECRC on the RX Path 160
- ECRC on the TX Path 161
- Debugging 163
- Setting Up Simulation 166
- Use Third-Party PCIe Analyzer 168
- BIOS Enumeration Issues 168
- Address[31:2] 169
- Figure A-6: I/O Read Request 171
- 7 6 5 4 3 2 1 0 175
- Core Config 8 4 1 175
- Additional Information 177
- Date Version Changes Made 178
- How to Contact Altera 182
- Typographic Conventions 182
- Visual Cue Meaning 183
Powiązane produkty i podręczniki dla Urządzenia pomiarowe Altera Stratix V Avalon-MM Interface for PCIe Solutions
Urządzenia pomiarowe Altera 10-Gbps Ethernet MAC MegaCore Function Instrukcja Użytkownika
(175 strony)
(175 strony)
Urządzenia pomiarowe Altera Triple Speed Ethernet MegaCore Function Instrukcja Użytkownika
(223 strony)
(223 strony)
Urządzenia pomiarowe Altera 8B10B Encoder/Decoder MegaCore Function Instrukcja Użytkownika
(32 strony)
(32 strony)
Urządzenia pomiarowe Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core Instrukcja Użytkownika
(11 strony)
(11 strony)
Urządzenia pomiarowe Altera Embedded Systems Development Kit, Cyclone III Edit Instrukcja Użytkownika
(82 strony)
(82 strony)
© 2020, manymanuals.pl. Wszelkie prawa zastrzeżone. | 0.039 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Komentarze do niniejszej Instrukcji