Altera Stratix V Avalon-MM Interface for PCIe Solutions Instrukcja Użytkownika Strona 97
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The TX TLP programming model scales with the data width. The Application Layer performs the same
writes for both the 64- and 128-bit interfaces. The Application Layer can only have one outstanding non-
posted request at a time. The Application Layer must use tags 16–31 to identify non-posted requests.
Note: For Root Ports, the Avalon-MM bridge does not filter Type 0 Configuration Requests by device
number. Application Layer software should filter out all requests to Avalon-MM Root Port
registers that are not for device 0. Application Layer software should return an Unsupported
Request Completion Status.
Sending a Write TLP
The Application Layer performs the following sequence of Avalon-MM accesses to the CRA slave port to
send a Memory Write Request:
1. Write the first 32 bits of the TX TLP to RP_TX_REG0.
2. Write the next 32 bits of the TX TLP to RP_TX_REG1.
3. Write the RP_TX_CNTRL.SOP to 1’b1 to push the first two dwords of the TLP into the Root Port TX
FIFO.
4. Repeat Steps 1 and 2. The second write to RP_TX_REG1 is required, even for three dword TLPs with
aligned data.
5. If the packet is complete, write RP_TX_CNTRL to 2’b10 to indicate the end of the packet. If the packet is
not complete, write 2’b00 to RP_TX_CNTRL.
6. Repeat this sequence to program a complete TLP.
When the programming of the TX TLP is complete, the Avalon-MM bridge schedules the TLP with
higher priority than TX TLPs coming from the TX slave port.
Sending a Read TLP or Receiving a Non-Posted Completion TLP
The TLPs associated with the Non-Posted TX requests are stored in the RP_RX_CPL FIFO buffer and
subsequently loaded into RP_RXCPL registers. The Application Layer performs the following sequence to
retrieve the TLP.
1. Polls the RP_RXCPL_STA TUS.SOP to determine when it is set to 1’b1.
2. Then RP_RXCPL_STATUS.SOP = 1’b’1, reads RP_RXCPL_REG0 and RP_RXCPL_REG1 to retrieve dword 0
and dword 1 of the TLP.
3. Read the RP_RXCPL_STATUS.EOP.
• If RP_RXCPL_STATUS.EOP = 1’b0, read RP_RXCPL_REG0 and RP_RXCPL_REG1 to retrieve dword 2
and dword 3 of the TLP, then repeat step 3.
• If RP_RXCPL_STATUS.EOP = 1’b1, read RP_RXCPL_REG0 and RP_RXCPL_REG1 to retrieve final
dwords of TLP.
PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
The Root Port supports MSI, MSI-X and legacy (INTx) interrupts. MSI and MSI-X interrupts are memory
writes from the Endpoint to the Root Port. MSI and MSI-X requests are forwarded to the interconnect
without asserting CraIrq_o.
5-28
Sending a Write TLP
UG-01097_avmm
2014.12.15
Altera Corporation
Registers
Send Feedback
- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Altera FPGA 8
- Debug Features 10
- IP Core Verification 10
- Recommended Speed Grades 11
- Running Qsys 14
- Generating the Example Design 15
- Simulating Altera Designs 17
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 19
- Programming a Device 20
- Parameter Settings 21
- Parameter Value Description 22
- Device Capabilities 25
- Error Reporting 26
- Link Capabilities 27
- MSI and MSI-X Capabilities 28
- Power Management 29
- Clock Domains on page 6-5 33
- Application Layer 34
- RX Avalon-MM Master Signals 36
- Clock Signals 41
- Signal Direction Description 42
- Variant Logical Interfaces 49
- Hard IP Status Extension 50
- Field and Bit Map 58
- 0134678951 58
- Bit(s) Field Description 59
- Serial Data Signals 60
- PIPE Interface Signals 64
- Test Signals 69
- Registers 70
- Altera-Defined VSEC Registers 78
- CvP Registers 79
- Address Range Register 83
- Bit Name Access Description 84
- Bits Name Access Description 85
- PCI Express Mailbox Registers 86
- Avalon-MM Mailbox Registers 90
- Address Name Access 91
- Description 91
- Byte Offset 91
- Register Dir Description 91
- Sending a Write TLP 97
- Root Port TLP Data Registers 99
- UG-01097_avmm 100
- 2014.12.15 100
- Related Information 101
- Bits Register Description 102
- Reset and Clocks 105
- Hard IP for PCI Express 106
- Example Design 106
- Clock Domains 109
- Data Rate Frequency 110
- Clock Summary 112
- Interrupts for Endpoints 113
- MSI/MSI‑X Support 115
- MsiIntfc_o[81:0] 116
- MsiControl_o[15:0] 116
- MsixIntfc_o[15:0] 116
- IntxReq_i 116
- IntxAck_o 116
- Error Handling 117
- Physical Layer Errors 118
- Data Link Layer Errors 118
- Transaction Layer Errors 119
- Error Type Description 120
- Status Bit Conditions 123
- IP Core Architecture 125
- Hard IP for PCI Express 126
- Top-Level Interfaces 127
- Avalon-MM Interface 127
- Clocks and Reset 127
- Transceiver Reconfiguration 127
- Interrupts 127
- Data Link Layer 128
- Altera Corporation 129
- Send Feedback 129
- Physical Layer 130
- TX Packets 131
- Avalon‑MM Bridge TLPs 135
- Byte Enable Value Description 136
- PCI Express Avalon-MM Bridge 138
- RX Block 144
- Avalon-MM RX Master Block 144
- TX Block 145
- Interrupt Handler Block 145
- Enable PLL calibration 147
- Throughput Optimization 151
- Throughput of Posted Writes 153
- Design Implementation 155
- CONF_DONE 156
- Endpoint Reset 156
- Root Port Reset 156
- SDC Timing Constraints 157
- Optional Features 159
- ECRC on the RX Path 160
- ECRC on the TX Path 161
- Debugging 163
- Setting Up Simulation 166
- Use Third-Party PCIe Analyzer 168
- BIOS Enumeration Issues 168
- Address[31:2] 169
- Figure A-6: I/O Read Request 171
- 7 6 5 4 3 2 1 0 175
- Core Config 8 4 1 175
- Additional Information 177
- Date Version Changes Made 178
- How to Contact Altera 182
- Typographic Conventions 182
- Visual Cue Meaning 183
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