Altera Transceiver Signal Integrity Instrukcja Użytkownika Pobierz pdf (Strona 5)

Contents v

February 2013 Altera Corporation Transceiver Signal Integrity Development Kit,

Stratix V GT Edition User Guide

Additional Information

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

1 2 3 4 5 6 7 8 9 10 ... 55 56

Feedback Subscribe 1
Contents 3
Additional Information 5
1. About This Kit 7
Software 8
Development Kit” on page 3–3 9
1–4 Chapter 1: About This Kit 10
Kit Features 10
2. Getting Started 11
Processing page 12
3. Software Installation 13
<install dir> 15
<version> 15
4. Development Board Setup 17
S5_UNLOCK 18
DPI6 18
DPI0 18
Note to: Table 4–5 20
5. Board Update Portal 23
6. Board Test System 25
Preparing the Board 26
Running the Board Test System 26
Using the Board Test System 27
Board Information 28
MAX II Registers 28
JTAG Chain 29
Qsys Memory Map 29
The GPIO Tab 30
The Flash Tab 31
The XFP/SFP+ Tab 33
The GXB SMA Tab 35
PMA Setting 36
Data Type 36
Error Control 37
Loopback 37
The Amphenol Tab 38
The Molex Tab 40
GTB MMPX Tab 42
Power Monitoring 44
The Clock Control 45
Serial Port Registers 46
Target Frequency 47
Set New Frequency 47
CFI Flash Memory Map 49
20A0000 50
./restore.sh r 52
Info–2 Additional Information 56
Typographic Conventions 56

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