Altera DE2-70 Dokumentacja Strona 1

1 Implementation of Web-Server Using Altera DE2-70 FPGA Development Kit A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENT OF FOR THE

10 We have used VHDL to enter the design in Quartus II. The entered circuit is compiled to generate the SRAM object file(.sof) needed to configu

11 SOPC Builder Altera’s Nios II is a soft processor is defined in a hardware description language. It can be implemented in Altera’s FPGA

12 • Examine a graphical view of an instruction trace that records the set of recently executed instructions. • Perform terminal input

13 LITERATURE REVIEW CHAPTER 2

14 Literature Review: FPGA development kits are generally used for basic logic implementations. Previously for web servers, computers were used that

15 METHODOLOGY AND PROBLEM FORMULATION CHAPTER 3

16 3.1 Nios II System: A Nios II system can be implemented on the DE2 board as shown in Fig 2

17 The Nios II processor and the interfaces needed to connect to other chips on the DE2 board are implemented in the Cyclone II FPGA chip. These co

18 3.2 Design Flow: SOPC builder tool of the Quartus II software is used for implementing the Nios II System. The different specifications for defi

19 Parallel Input Output(I): Width: 8 bits Direction: input ports only Parallel Input Output(II): Width: 8 bits Direction: output ports only JTAG UA

2 NATIONAL INSTITUTE OF TECHNOLOGY ROURKELA CERTIFICATE This is to certify that the thesis entitled, “Implementation of Web-Server Using Al

20  Having specified all components needed to implement the desired system, it can now be generated. Select the System Generation tab.Turn off Si

21 3.3 Integration of the Nios II System into a Quartus II Project To complete the hardware design, we have to perform the following: • Instantiate

22 The VHDL code produced by the SOPC is quite large. The portion of code that defines port signals for entity nios_system is shown as: entity nios

23 3.3.2 A top-level VHDL entity that instantiates the Nios II system(for light control circuit): −− Implements a simple Nios II system for the DE2

24 END lights; ARCHITECTURE Structure OF lights IS COMPONENT nios_system PORT ( clk : IN STD_LOGIC; reset_n : IN STD_LOGIC; out_port_from_the_LEDs :

25 3.3.3 Compiling the generated code along with top level VHDL entity: Add this file and all the *.vhd files produced by the SOPC Builder

26 4. The configuration file lights.sof should be listed in the window. If the file is not already listed, then add this file. 5. Click the box under Pr

27 3.5 Running the Application Program: Having configured the required hardware in the FPGA device, it is now necessary to create and execute an appli

28 The program loads the addresses of the Data registers in the two PIOs into processor registers r2 and r3. It then has an infinite loop that merely

29 This software needs to know the characteristics of the designed Nios II system, which are given in the ptf file nios_system.ptf. Click the Nios

3 ACKNOWLEDGEMENT I avail this opportunity to

30 3.6.1 Compiling and loading the program: After successfully creating a project, the program can be compiled and downloaded onto the DE2 board. The

31 RESULT and DISCUSSIONS CHAPTER 4

32 Result and Discussions: The Nios II system was programmed and configured in the board successfully. This system can now be developed for any des

33 References

34 References: [1] www.altera.com › Products › Literature. [2]www.smdp.iitkgp.ernet.in/PDF%5CVLSI_DSP%5CEmbedded_System_Design.pdf. [3] http://www.ni

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4 Contents SI. No. Topic Page No. 1. Chapter 1: Introduction 5-12 2. Chapter 2: Literature review 13-14 3. Chapter 3: Methodology a

5 ABSTRACT A web server is a computer program that delivers (serves) content, such as web pages, to the Clients. A field-programmable gate array (F

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7 Introduction: FPGA & Altera’s DE270 FPGA Development Board A field-programmable gate array (FPGA) is an integrated circuit designed to

8 Quartus II Quartus II is a CAD system used to implement circuits in an Altera FPGA device. The Quartus II system includes full support for all of

9 The CAD flow involves the following steps: Design Entry – the desired circuit is specified either by means of a schematic diagram, or by using a har