Altera DE2-70 Dokumentacja Pobierz pdf (Strona 22)

The VHDL code produced by the SOPC is quite large. The portion of code that defines port

signals for entity nios_system is shown as:

entity nios_system is

port(

--1) global signals

signal clk : IN STD_LOGIC;

signal reset_n : IN STD_LOGIC;

--2) LEDs

signal out_port_from _the_LEDs : OUT STD_LOGIC_VECTOR(7 DOWN TO 0);

signal in_from_the_switches : IN STD_LOGIC_VECTOR(7 DOWN TO 0);

);

end entity nios_system;

The 8-bit vector that is the input to the parallel port Switches is called in_port_to_the_Switches.

The 8-bit output vector is called out_port_from_the_LEDs. The clock and reset signals are

called clk and reset_n, respectively. The reset signal is added automatically by the SOPC

Builder; it is called reset_n because it is active low.

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Altera DE2-70 Dokumentacja Strona 22