Altera DE2-115 Instrukcja Użytkownika Strona 43

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Figure 4-14 LVDS interface on HSMC connector and Cyclone IV E FPGA
Table 4-9 Pin Assignments for HSMC connector
Signal Name
FPGA Pin
No.
Description I/O Standard
HSMC_CLKIN0 PIN_AH15
Dedicated clock input
Depending
on JP6
HSMC_CLKIN_N1 PIN_J28
LVDS RX or CMOS input or differential clock input
Depending
on JP7
HSMC_CLKIN_N2 PIN_Y28
LVDS RX or CMOS input or differential clock input
Depending
on JP7
HSMC_CLKIN_P1 PIN_J27
LVDS RX or CMOS input or differential clock input
Depending
on JP7
HSMC_CLKIN_P2 PIN_Y27
LVDS RX or CMOS input or differential clock input
Depending
on JP7
HSMC_CLKOUT0 PIN_AD28
Dedicated clock output
Depending
on JP7
HSMC_CLKOUT_N1
PIN_G24
LVDS TX or CMOS I/O or differential clock output
Depending
on JP7
HSMC_CLKOUT_N2
PIN_V24
LVDS TX or CMOS I/O or differential clock output
Depending
on JP7
HSMC_CLKOUT_P1
PIN_G23
LVDS TX or CMOS I/O or differential clock output
Depending
on JP7
HSMC_CLKOUT_P2
PIN_V23
LVDS TX or CMOS I/O or differential clock output
Depending
on JP7
HSMC_D[0] PIN_AE26
LVDS TX or CMOS I/O Depending
on JP7
HSMC_D[1] PIN_AE28
LVDS RX or CMOS I/O Depending
on JP7
HSMC_D[2] PIN_AE27
LVDS TX or CMOS I/O Depending
on JP7
HSMC_D[3] PIN_AF27
LVDS RX or CMOS I/O Depending
on JP7
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