Altera DE2-115 Instrukcja Użytkownika Pobierz pdf (Strona 51)

GPIO[22] PIN_AG25 GPIO Connection DATA[22] Depending on JP6

GPIO[23] PIN_AD25 GPIO Connection DATA[23] Depending on JP6

GPIO[24] PIN_AH25 GPIO Connection DATA[24] Depending on JP6

GPIO[25] PIN_AE25 GPIO Connection DATA[25] Depending on JP6

GPIO[26] PIN_AG22 GPIO Connection DATA[26] Depending on JP6

GPIO[27] PIN_AE24 GPIO Connection DATA[27] Depending on JP6

GPIO[28] PIN_AH22 GPIO Connection DATA[28] Depending on JP6

GPIO[29] PIN_AF26 GPIO Connection DATA[29] Depending on JP6

GPIO[30] PIN_AE20 GPIO Connection DATA[30] Depending on JP6

GPIO[31] PIN_AG23 GPIO Connection DATA[31] Depending on JP6

GPIO[32] PIN_AF20 GPIO Connection DATA[32] Depending on JP6

GPIO[33] PIN_AH26 GPIO Connection DATA[33] Depending on JP6

GPIO[34] PIN_AH23 GPIO Connection DATA[34] Depending on JP6

GPIO[35] PIN_AG26 GPIO Connection DATA[35] Depending on JP6

The DE2-115 Board provides 14-pin expansion header. The header connects directly to 7 pins of the

Cyclone IV E FPGA, and also provides DC +3.3V (VCC3P3), and six GND pins as shown in

Figure 4-20. The voltage level of the I/O pins on the 14-pin expansion header is 3.3V. Finally,

Table 4-13 shows the pin assignments for I/O connections.

Figure 4-20 Connections between FPGA and 14-pin general purpose I/O

Table 4-13 Pin Assignments for General Purpose I/Os

Signal Name FPGA Pin No. Description I/O Standard

EX_IO[0] PIN_J10 Extended IO[0] 3.3V

EX_IO[1] PIN_J14 Extended IO[1] 3.3V

EX_IO[2] PIN_H13 Extended IO[2] 3.3V

1 2 ... 46 47 48 49 50 51 52 53 54 55 56 ... 120 121

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Altera DE2-115 Instrukcja Użytkownika Strona 51