Altera DE2-115 Instrukcja Użytkownika Pobierz pdf (Strona 58)

There is one jumper for each chip for switching work modes from RGMII to MII (See Figure 4-28).

You will need to perform a hardware reset after any change for enabling new settings. Table 4-21

and Table 4-22 describe the working mode settings for ENET0 PHY (U8) and ENET1 PHY (U9)

respectively.

In addition, it is dynamically configurable to support 10Mbps, 100Mbps (Fast Ethernet) or

1000Mbps (Gigabit Ethernet) operation using standard Cat 5e UTP cabling. The associated pin

assignments are listed in Table 4-23. For detailed information on how to use the 88E1111 refers to

its datasheet and application notes, which are available on the manufacturer’s website.

Figure 4-27 Connections between FPGA and Ethernet

Figure 4-28 Working mode setup header for Ethernet PHY

1 2 ... 53 54 55 56 57 58 59 60 61 62 63 ... 120 121

Brak uwag

Altera DE2-115 Instrukcja Użytkownika Strona 58