Altera Arria V GX FPGA Development Board Instrukcja Użytkownika Strona 28

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2–18 Chapter 2: Board Components
Configuration, Status, and Setup Elements
Arria V GX FPGA Development Board November 2013 Altera Corporation
Reference Manual
Figure 2–5 shows the PFL configuration.
f For information on the flash memory map storage, refer to the refer to the Arria V GX
FPGA Development Kit, User Guide.
There are two pages reserved for the FPGA configuration data. The factory hardware
page—page 0—loads upon power-up when the
Factory1
DIP switch (SW5.3) is set to
'1'. Otherwise, the user hardware page 1 loads. Pressing the
PGM1_CONFIG
push button
(S3) loads the FPGA with a hardware page based on which
PGM1_LED[2:0]
LED (D12,
D13, D14) illuminates.
Figure 2–5. PFL Configuration
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