Altera Arria V GX FPGA Development Board Instrukcja Użytkownika Pobierz pdf (Strona 74)

2–64 Chapter 2: Board Components

Memory

Arria V GX FPGA Development Board November 2013 Altera Corporation

Reference Manual

DDR3B_A13

P31 1.5-V SSTL Class I Address bus

DDR3B_BA0

M32 1.5-V SSTL Class I Bank address bus

DDR3B_BA1

N32 1.5-V SSTL Class I Bank address bus

DDR3B_BA2

J34 1.5-V SSTL Class I Bank address bus

DDR3B_CASN

L33 1.5-V SSTL Class I Row address select

DDR3B_CKE

E31 1.5-V SSTL Class I Column address select

DDR3B_CLK_N

C30 1.5-V SSTL Class I Differential output clock

DDR3B_CLK_P

B30 1.5-V SSTL Class I Differential output clock

DDR3B_CSN

L34 1.5-V SSTL Class I Chip select

DDR3B_ODT

L31 1.5-V SSTL Class I On-die termination enable

DDR3B_RASN

K34 1.5-V SSTL Class I Row address select

DDR3B_RESETN

G30 1.5-V SSTL Class I Reset

DDR3B_WEN

M33 1.5-V SSTL Class I Write enable

DDR3B_ZQ2

— 1.5-V SSTL Class I ZQ impedance calibration

DDR3B (U6)

DDR3B_DM0

J30 1.5-V SSTL Class I Write mask byte lane

DDR3B_DM1

J29 1.5-V SSTL Class I Write mask byte lane

DDR3B_DQ0

B28 1.5-V SSTL Class I Data bus byte lane

DDR3B_DQ1

C29 1.5-V SSTL Class I Data bus byte lane

DDR3B_DQ2

R30 1.5-V SSTL Class I Data bus byte lane

DDR3B_DQ3

A29 1.5-V SSTL Class I Data bus byte lane

DDR3B_DQ4

A28 1.5-V SSTL Class I Data bus byte lane

DDR3B_DQ5

L30 1.5-V SSTL Class I Data bus byte lane

DDR3B_DQ6

D30 1.5-V SSTL Class I Data bus byte lane

DDR3B_DQ7

D29 1.5-V SSTL Class I Data bus byte lane

DDR3B_DQ8

L28 1.5-V SSTL Class I Data bus byte lane

DDR3B_DQ9

M28 1.5-V SSTL Class I Data bus byte lane

DDR3B_DQ10

H28 1.5-V SSTL Class I Data bus byte lane

DDR3B_DQ11

C28 1.5-V SSTL Class I Data bus byte lane

DDR3B_DQ12

D28 1.5-V SSTL Class I Data bus byte lane

DDR3B_DQ13

F28 1.5-V SSTL Class I Data bus byte lane

DDR3B_DQ14

M29 1.5-V SSTL Class I Data bus byte lane

DDR3B_DQ15

N29 1.5-V SSTL Class I Data bus byte lane

DDR3B_DQS_N0

P30 1.5-V SSTL Class I Data strobe N byte lane

DDR3B_DQS_N1

T29 1.5-V SSTL Class I Data strobe N byte lane

DDR3B_DQS_P0

N30 1.5-V SSTL Class I Data strobe P byte lane

DDR3B_DQS_P1

R29 1.5-V SSTL Class I Data strobe P byte lane

DDR3B (U12)

DDR3B_DM2

J30 1.5-V SSTL Class I Write mask byte lane

Table 2–55. DDR3 x32 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)

Board Reference

Schematic

Signal Name

Arria V GX FPGA

Pin Number

I/O Standard Description

1 2 ... 69 70 71 72 73 74 75 76 77 78 79 ... 89 90

Komentarze do niniejszej Instrukcji

Brak uwag

Altera Arria V GX FPGA Development Board Instrukcja Użytkownika Strona 74

Komentarze do niniejszej Instrukcji

Powiązane produkty i podręczniki dla Urządzenia pomiarowe Altera Arria V GX FPGA Development Board