Altera Arria V GX FPGA Development Board Instrukcja Użytkownika Pobierz pdf (Strona 6)

1–2 Chapter 1: Overview

Board Component Blocks

Arria V GX FPGA Development Board November 2013 Altera Corporation

Reference Manual

Board Component Blocks

The development board features the following major component blocks:

■ Two Arria V GX FPGA 5AGXFB3HF40 in the 1517-pin FineLine BGA (FBGA)

package

■ 362 LEs

■ 136,880 adaptive logic modules (ALMs)

■ 17,260 Kbit (Kb) M10K on-die memory

■ 2,098 Kb MLAB memory

■ 24 6-Gbps transceivers

■ 12 phase locked loops (PLLs)

■ 2,090 18x18 multipliers

■ 1.1-V core voltage

■ MAX

II CPLD EPM2210GF324 System Controller in the 324-pin FBGA package

■ FPGA configuration circuitry

■ MAX

II CPLD EPM570GM100 and flash fast passive parallel (FPP)

configuration

■ On-board USB-Blaster

II for use with the Quartus

II Programmer

■ Clocking circuitry

■ Nine on-board oscillators

■ One 50-MHz oscillator

■ Two 125-MHz oscillators

■ Clock buffer with six outputs sourced by SMA or programmable oscillator

with a default frequency of 100-MHz

■ One programmable oscillator with a default frequency of 148.5-MHz

■ Four programmable oscillators with four outputs each of various default

frequencies

■ Clock buffer with two outputs sourced by one of the above four

programmable oscillators with one output to the FPGA reference clock and

Bull's Eye

SMA

■ SMA connectors for external LVPECL clock input

■ Power supply

■ 14-V – 20-V DC input

■ PCI Express edge connector power

■ 12-V PCI Express ATX supply

■ On-board power measurement circuitry

1 2 3 4 5 6 7 8 9 10 11 ... 89 90

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