Altera CPRI v6.0 MegaCore Function Instrukcja Użytkownika Strona 57
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Figure 3-19: Direct RTVS TX Timing Diagram
Expected behavior on the direct RTVS TX interface of a CPRI v6.0 IP core running at 10.1376 Gbps.
The aux_tx_x and aux_tx_seq signals are not part of this interface and are available only if you turn on
the AUX interface in your CPRI v6.0 IP core variation. However, their presence in the timing diagram
explains the timing of the rtvs_tx_ready output signal that you use to identify the clock cycles when you
can write RTVS data to the CPRI frame.
Note that the write latency is one cpri_clkout clock cycle in this example.
cpri_clkout
100 101 124
7
4
6
aux_tx_x
aux_tx_seq
rtvs_tx_ready
rtvs_tx_valid
X
D1D2D3D4
Xrtvs_tx_data[31:0]
54
3
21
0
79
3
21
0
Auxiliary latency cycle(s) == 0
Related Information
Avalon Interface Specifications
For more information about the Avalon-ST protocol, including timing diagrams, refer to the Avalon
Streaming Interfaces chapter.
Direct HDLC Serial Interface
If you turn on Enable direct HDLC serial interface in the CPRI v6.0 parameter editor, the direct HDLC
serial interface is available. This interface allows direct access to the slow control and management data in
the CPRI frame. You can connect this interface to a user-defined HDLC PCS and MAC.
This interface is Avalon-ST compliant with a read latency value of 1.
You can alter the transmit write latency with the Auxiliary latency cycle(s) parameter. However, you do
not need to view the aux_tx_seq signal for correct alignment. You can monitor the hdlc_rx_valid and
hdlc_tx_ready signals to discover the correct times to read and write data on this interface.
Table 3-9: Direct HDLC Serial Interface Signals
All interface signals are clocked by the cpri_clkout clock.
Direct HDLC Serial RX Interface
Signal Name Direction Description
hdlc_rx_valid Output When asserted, indicates hdlc_rx_data holds a valid
HDLC bit in the current clock cycle.
UG-01156
2014.08.18
Direct HDLC Serial Interface
3-27
Functional Description
Altera Corporation
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About the CPRI v6.0 IP Core 5
- Device Family Support 7
- IP Core Verification 8
- Release Information 10
- Related Information 11
- Installation and Licensing 13
- 2014.08.18 14
- File Name Description 15
- CPRI v6.0 IP Core Parameters 18
- Parameter Range Default 20
- Parameter Description 20
- Adding the Clean-Up PLL 23
- Adding the External TX PLL 24
- Simulating Altera IP Cores 27
- Understanding the Testbench 28
- Running the Testbench 28
- Parameter Value 29
- Functional Description 31
- Information 35
- AUX Interface 39
- AUX Interface Signals 40
- AUX RX Interface Data Signals 41
- AUX TX Interface Data Signals 42
- AUX Interface Synchronization 47
- Auxiliary Latency Cycles 47
- Direct IQ Interface 51
- Direct HDLC Serial Interface 57
- RX MII Signals 62
- TX MII Signals 63
- MII Status Signals 64
- CPU Interface Signals 66
- Specifying the Control Word 67
- Auto-Rate Negotiation 70
- Extended Delay Measurement 71
- Resolution 72
- Deterministic Latency 73
- CPRI Link 75
- Interface to the External PLL 78
- Testing Features 79
- CPRI v6.0 IP Core Signals 82
- Clock Name 86
- Direction 86
- CPRI v6.0 IP Core Registers 90
- 2015.02.16 91
- INTR Register 92
- L1_STATUS Register 92
- L1_CONFIG Register 93
- BIT_RATE_CONFIG Register 94
- PROT_VER Register 95
- TX_SCR Register 96
- RX_SCR Register 96
- CM_CONFIG Register 97
- CM_STATUS Register 98
- START_UP_SEQ Register 98
- START_UP_TIMER Register 99
- FLSAR Register 100
- CTRL_INDEX Register 100
- TX_CTRL Register 101
- RX_CTRL Register 102
- RX_ERR Register 102
- LOOPBACK Register 103
- RX_BFN Register 103
- Bits Field Name Type Value on 104
- Description 104
- TX_DELAY Register 105
- RX_DELAY Register 106
- TX_EX_DELAY Register 107
- RX_EX_DELAY Register 107
- ROUND_TRIP_DELAY Register 108
- XCVR_BITSLIP Register 108
- UG-01156 110
- Subscribe 110
- Send Feedback 110
- Altera Corporation 112
- Additional Information 113
- How to Contact Altera 114
- Typographic Conventions 114
- Visual Cue Meaning 115
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