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Signal Name Direction Description
reconfig_clk Input
Arria V GZ and Stratix V transceiver reconfiguration
interface
These signals are present only in P core variations that
target an Arria V GZ or Stratix V device.
reconfig_to_xcvr[69:0] Input
reconfig_from_xcvr[45:0] Output
reconfig_clk Input
Arria 10 transceiver reconfiguration interface
These signals are present only in P core variations that
target an Arria 10 device.
reconfig_reset Input
reconfig_write
Input
reconfig_read
Input
reconfig_address[9:0]
Input
reconfig_writedata[31:0]
Input
reconfig_readdata[31:0]
Output
reconfig_waitrequest
Output
xcvr_tx_analogreset
Input
Interface to external reset controller
xcvr_tx_digitalreset
Input
xcvr_tx_cal_busy
Output
xcvr_rx_analogreset
Input
xcvr_rx_digitalreset
Input
xcvr_rx_cal_busy
Output
xcvr_reset_tx_ready
Input
xcvr_reset_rx_ready
Input
xcvr_ext_pll_clk Input Interface to external TX PLL
xcvr_rx_is_lockedtoref Output
Transceiver debug interface
These signals are present only if you turn on Enable
debug interface in the CPRI v6.0 parameter editor.
xcvr_rx_is_lockedtodata Output
xcvr_rx_errdetect[3:0] Output
xcvr_rx_disperr[3:0] Output
xcvr_rx_blk_sh_err Output
UG-01156
2014.08.18
CPRI v6.0 IP Core Transceiver and Transceiver Management Signals
4-7
CPRI v6.0 IP Core Signals
Altera Corporation
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About the CPRI v6.0 IP Core 5
- Device Family Support 7
- IP Core Verification 8
- Release Information 10
- Related Information 11
- Installation and Licensing 13
- 2014.08.18 14
- File Name Description 15
- CPRI v6.0 IP Core Parameters 18
- Parameter Range Default 20
- Parameter Description 20
- Adding the Clean-Up PLL 23
- Adding the External TX PLL 24
- Simulating Altera IP Cores 27
- Understanding the Testbench 28
- Running the Testbench 28
- Parameter Value 29
- Functional Description 31
- Information 35
- AUX Interface 39
- AUX Interface Signals 40
- AUX RX Interface Data Signals 41
- AUX TX Interface Data Signals 42
- AUX Interface Synchronization 47
- Auxiliary Latency Cycles 47
- Direct IQ Interface 51
- Direct HDLC Serial Interface 57
- RX MII Signals 62
- TX MII Signals 63
- MII Status Signals 64
- CPU Interface Signals 66
- Specifying the Control Word 67
- Auto-Rate Negotiation 70
- Extended Delay Measurement 71
- Resolution 72
- Deterministic Latency 73
- CPRI Link 75
- Interface to the External PLL 78
- Testing Features 79
- CPRI v6.0 IP Core Signals 82
- Clock Name 86
- Direction 86
- CPRI v6.0 IP Core Registers 90
- 2015.02.16 91
- INTR Register 92
- L1_STATUS Register 92
- L1_CONFIG Register 93
- BIT_RATE_CONFIG Register 94
- PROT_VER Register 95
- TX_SCR Register 96
- RX_SCR Register 96
- CM_CONFIG Register 97
- CM_STATUS Register 98
- START_UP_SEQ Register 98
- START_UP_TIMER Register 99
- FLSAR Register 100
- CTRL_INDEX Register 100
- TX_CTRL Register 101
- RX_CTRL Register 102
- RX_ERR Register 102
- LOOPBACK Register 103
- RX_BFN Register 103
- Bits Field Name Type Value on 104
- Description 104
- TX_DELAY Register 105
- RX_DELAY Register 106
- TX_EX_DELAY Register 107
- RX_EX_DELAY Register 107
- ROUND_TRIP_DELAY Register 108
- XCVR_BITSLIP Register 108
- UG-01156 110
- Subscribe 110
- Send Feedback 110
- Altera Corporation 112
- Additional Information 113
- How to Contact Altera 114
- Typographic Conventions 114
- Visual Cue Meaning 115
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