Altera Cyclone V E FPGA Development Board Instrukcja Użytkownika Pobierz pdf (Strona 22)

2–14 Chapter 2: Board Components

FPGA Configuration

Cyclone V E FPGA Development Board March 2013 Altera Corporation

Reference Manual

Figure 2–4 shows the PFL configuration.

f For more information on the following topics, refer to the respective documents:

■ Board Update Portal, PFL design, and flash memory map storage, refer to the

Cyclone V E FPGA Development Kit User Guide.

■ PFL megafunction, refer to Parallel Flash Loader Megafunction User Guide.

FPGA Programming over External USB-Blaster

The JTAG chain header provides another method for configuring the FPGA using an

external USB-Blaster device with the Quartus II Programmer running on a PC. To

prevent contention between the JTAG masters, the embedded USB-Blaster is

automatically disabled when you connect an external USB-Blaster to the JTAG chain

through the JTAG chain header.

Figure 2–4. PFL Configuration

MAX V CPLD

5M2210 System Controller

FPGA_DATA [0]

FPGA_DCLK

FLASH_A [25:1]

FLASH_D [15:0]

DATA [0]

DCLK

nSTATUS

nCONFIG

CONF_DONE

MSEL[4:0]

2.5 V

10 kΩ

nCE

CFI Flash

FLASH_CEn

FLASH_OEn

FLASH_WEn

FLASH_A [25:0]

FLASH_D [15:0]

FLASH_CEn

FLASH_OEn

FLASH_WEn

FLASH_WPn

FLASH_ADVn

FPGA_nCONFIG

FPGA_CONF_DONE

FLASH_RYBSYn

FPGA_nSTATUS

2.5 V

10 kΩ

FLASH_ADVn

CONF_DONE_LED

2.5 V

FLASH_CLK

FLASH_RSTn

FLASH_RESETn

PS PORT

Flash Interface

56.2 Ω

100 Ω56.2 Ω

56.2 Ω

50 MHz

100 MHz

INIT_DONE

FPGA_INIT_DONE

2.5 V

2.5 V 2.5 V

ERROR

LOAD

MAX_CONF_DONE1

SEC_MODE

FACT_LOAD

CLK_EN

CLK_SEL

MAX_RESETn

PGM_CONFIG

PGM_SEL

PGM_LED0

PGM_LED1

PGM_LED2

DIP Switch

10 kΩ

Cyclone V FPGA

DIP Switch

1 2 ... 17 18 19 20 21 22 23 24 25 26 27 ... 55 56

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