Altera Cyclone V E FPGA Development Board Instrukcja Użytkownika Pobierz pdf (Strona 26)

2–18 Chapter 2: Board Components

Clock Circuitry

Cyclone V E FPGA Development Board March 2013 Altera Corporation

Reference Manual

MAX V Reset Push Button

The MAX V reset push button,

MAX_RESETn

(S3), is an input to the MAX V CPLD

5M2210 System Controller. This push button is the default reset for the CPLD logic.

Program Configuration Push Button

The program configuration push button,

PGM_CONFIG

(S1), is an input to the MAX V

CPLD 5M2210 System Controller. This input forces a FPGA reconfiguration from the

flash memory. The location in the flash memory is based on the settings of

PGM_LED[2:0]

, which is controlled by the program select push button,

PGM_SEL

. Valid

settings include

PGM_LED0

PGM_LED1

, or

PGM_LED2

on the three pages in flash memory

reserved for FPGA designs.

Program Select Push Button

The program select push button,

PGM_SEL

(S2), is an input to the MAX V CPLD

5M2210 System Controller. This push button toggles the

PGM_LED[2:0]

sequence that

selects which location in the flash memory is used to configure the FPGA. Refer to

Table 2–6 for the

PGM_LED[2:0]

sequence definitions.

Clock Circuitry

This section describes the board's clock inputs and outputs.

On-Board Oscillators

The development board include oscillators with a frequency of 50-MHz, 100-MHz,

and a programmable oscillator.

1 2 ... 21 22 23 24 25 26 27 28 29 30 31 ... 55 56

Brak uwag

Altera Cyclone V E FPGA Development Board Instrukcja Użytkownika Strona 26