Altera DSP Development Kit, Stratix V Edition Instrukcja Użytkownika Pobierz pdf (Strona 44)

6–20 Chapter 6: Board Test System

Using the Board Test System

DSP Development Kit, Stratix V Edition July 2013 Altera Corporation

User Guide

■ Pattern sync—Shows the pattern synced or not synced state. The pattern is

considered synced when the start of the data sequence is detected after channel

lock is acquired.

Port

The Port control allows you to specify which interface to test. The following port tests

are available:

■ SMA x1 (10 Gbps+)

PMA Setting

The PMA Setting button allows you to make changes to the PMA parameters that

affect the active transceiver interface.

1 For loopback testing, use the PMA button to place the Stratix V FPGA in serial

loopback mode.

The following settings are available for analysis:

■ Serial Loopback—Routes signals between the transmitter and the receiver. Enter

the following values to enable the serial loopbacks:

= High speed serial transceiver signals to observe to 10 Gbps+ high-speed

transmit data signal

= Serial loopback

■ VOD—Specifies the voltage output differential of the transmitter buffer.

■ Pre-emphasis tap

■ Pre—Specifies the amount of pre-emphasis on the pre-tap of the transmitter

buffer.

■ First post—Specifies the amount of pre-emphasis on the first post tap of the

transmitter buffer.

■ Second post—Specifies the amount of pre-emphasis on the second post tap of

the transmitter buffer.

■ Equalizer—Specifies the setting for the receiver equalizer.

■ DC gain—Specifies the DC portion of the receiver equalizer.

Data Type

The Data type control specifies the type of data contained in the transactions. The

following data types are available for analysis:

■ PRBS 7—Selects pseudo-random 7-bit sequences.

■ PRBS 15—Selects pseudo-random 15-bit sequences.

■ PRBS 23—Selects pseudo-random 23-bit sequences.

■ PRBS 31—Selects pseudo-random 31-bit sequences.

■ HF—Selects highest frequency divide-by-2 data pattern "10101010"

■ HF1—Selects next highest frequency divide-by-6 data pattern "111000111000"

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Altera DSP Development Kit, Stratix V Edition Instrukcja Użytkownika Strona 44