Altera Integer Arithmetic IP Instrukcja Użytkownika Strona 1

Integer Arithmetic IP Cores User GuideSubscribeSend FeedbackUG-010632014.12.19101 Innovation DriveSan Jose, CA 95134www.altera.com

1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.The parameter editor appears.2. Specify a t

Parameter Name Type Required DescriptionCOEF1_[] Integer No Specifies the coefficient value[0..7] for the inputs of thesecond multiplier. Thenumber of

Figure 8-2: ALTMULT_ACCUM Simulation Results8-20Understanding the Simulation ResultsUG-010632014.12.19Altera CorporationALTMULT_ACCUM (Multiply-Accumu

ALTMULT_ADD (Multiply-Adder)92014.12.19UG-01063SubscribeSend FeedbackThe ALTMULT_ADD megafunction allows you to implement a multiplier-adder.The follo

Figure 9-1: ALTMULT_ADD Portsdataa[]instALTMULT_ADDdatab[]signascanouta[]signbscanoutb[]result[]overflowmult_is_saturatedchain_out_sat_overflowaclr0ac

The multipliers and adders of the ALTMULT_ADD megafunction are placed in the dedicated DSP blockcircuitry of the Stratix devices. If all of the input

Pre-adderWith pre-adder, additions or subtractions are done prior to feeding the multiplier.There are five pre-adder modes:• Simple mode• Coefficient

Figure 9-3: Pre-adder Coefficient Modea0b0Mult0resultcoef+/-Preaddercoefsel0Pre-adder Input ModeIn this mode, one multiplier operand derives from the

This mode is expressed in the following equation.The following shows the pre-adder square mode of two multipliers.Figure 9-5: Pre-adder Square Modea0b

Systolic Delay RegisterIn a systolic architecture, the input data is fed into a cascade of registers acting as a data buffer. Eachregister delivers an

Figure 9-8: Systolic Delay Register Implementation of 2 Multipliersa0b0Mult0resultchainina1b1Mult1+/-+/-Systolic registersThe sum of two multipliers i

Figure 1-4: IP Parameter EditorView IP portand parameter detailsApply preset parameters forspecific applicationsSpecify your IP variation nameand targ

Figure 9-9: Systolic Delay Register Implementation of 4 Multipliersa0b0Mult0resultchaininchainina1b1Mult1a2b2Mult2a3b3Mult3result+/-+/-+/-+/-Systolic

The following lists the advantages of systolic register implementation:• Reduces DSP resource usage• Enables efficient mapping in the DSP block using

The following figure shows the double accumulator implementation.Figure 9-12: Double Accumulatora0b0a1b1Mult0Mult1Accumulator feedba ckOutput result+

To view the VHDL component declaration for the megafunction, refer to the VHDL Design File (.vhd)altera_mf_components.vhd in the <Quartus II instal

Port Name Required Descriptionoutput_round No Enables dynamically controlled output rounding. When OUTPUT_ROUNDING is set to VARIABLE, output_round en

Port Name Required Descriptionscanouta[] No Output of scan chain A. Output port [WIDTH_A - 1..0]wide. When designing with Stratix III devices, port ca

Parameter Name Type RequiredDescriptionINPUT_REGISTER_A1 String No Specifies the clock port for thedataa[] operand of the secondmultiplier. Values are

Parameter Name Type RequiredDescriptionINPUT_REGISTER_B1 String No Specifies the clock port for thedatab[] operand of the secondmultiplier. Values are

Parameter Name Type RequiredDescriptionINPUT_ACLR_A2 String No Specifies the asynchronous clearfor the dataa[] operand of thethird multiplier. Values

Parameter Name Type RequiredDescriptionINPUT_SOURCE_A0 String No Specifies the data source to thefirst multiplier. Values are DATAAand SCANA. If this

Figure 1-5: Legacy Parameter EditorsLegacy parameter editors1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP c

Parameter Name Type RequiredDescriptionINPUT_SOURCE_A3 String No Specifies the data source to thefourth and correspondingmultiplier. Values are DATAA

Parameter Name Type RequiredDescriptionINPUT_SOURCE_B2 String No Specifies the data source of thethird multiplier. Values are DATABand SCANB. If this

Parameter Name Type RequiredDescriptionREPRESENTATION_A String No Specifies the numerical represen‐tation of the multiplier input A.Values are UNSIGNE

Parameter Name Type RequiredDescriptionSIGNED_PIPELINE_REGISTER_[] String No Parameter [A,B]. Specifies theclock signal for the secondregister on the

Parameter Name Type RequiredDescriptionMUTIPLIER1_DIRECTION String No Specifies whether the secondmultiplier adds or subtracts itsvalue from the sum.

Parameter Name Type RequiredDescriptionEXTRA_LATENCY String No Specifies the number of clockcycles of latency.LPM_HINT String NoWhen you instantiate a

Table 9-8: ALTMULT_ADD Megafunction Parameters (Stratix II, Stratix III, and Stratix IV Devices Only)Parameter Name Type RequiredDescriptionOUTPUT_SAT

Parameter Name Type RequiredDescriptionOUTPUT_ROUNDING String No Enables rounding handling atsecond adder stage. If originaldesign uses a Stratix II d

Parameter Name Type RequiredDescriptionOUTPUT_SATURATION String No Enables saturation handling atsecond adder stage. If originaldesign uses a Stratix

Parameter Name Type RequiredDescriptionCHAINOUT_ROUNDING String NoEnables rounding handling at thechainout stage. Values are YES,NO, and VARIABLE. A v

Figure 1-6: IP Core Generated FilesNotes:1. If supported and enabled for your IP variation2. If functional simulation models are generated<Project

Parameter Name Type RequiredDescriptionCHAINOUT_ROUND_OUTPUT_ACLR String No Specifies the asynchronous clearsource for the third register onthe chaino

Parameter Name Type RequiredDescriptionCHAINOUT_SATURATE_OUTPUT_ACLR String No Specifies the asynchronous clearsource for the third register onthe cha

Parameter Name Type RequiredDescriptionZERO_LOOPBACK_OUTPUT_REGISTER String No Specifies the clock source for thethird register on the zero_loopback i

Parameter Name Type RequiredDescriptionSHIFT_MODE String NoSpecifies the shift mode. Valuesare NO, LEFT, RIGHT, ROTATION,and VARIABLE. If VARIABLE iss

Parameter Name Type RequiredDescriptionROTATE_OUTPUT_ACLR String No Specifies the asynchronous clearsource for the third register onthe rotate input.

Parameter Name Type RequiredDescriptionPORT_OUTPUT_IS_OVERFLOW String No Specifies port usage. Values arePORT_UNUSED and PORT_USED.When the value is s

This design example uses the ALTMULT_ADD megafunction to implement a simple FIR filter as shownin the following equation. This example uses the MegaWi

Figure 9-13: ALTMULT_ADD Simulation Results9-36Understanding the Simulation ResultsUG-010632014.12.19Altera CorporationALTMULT_ADD (Multiply-Adder)Sen

ALTMULT_COMPLEX (Complex Multiplier)102014.12.19UG-01063SubscribeSend FeedbackThe ALTMULT_COMPLEX megafunction implements the multiplication of two co

Figure 10-1: ALTMULT_COMPLEX Portsdataa_realinstALTMULT_COMPLEXdatab_realdataa_imagresult_realdatab_imagclockenaaclrresult_imagComplex MultiplicationC

compile the IP variation in the current version of the Quartus II software. Many Altera IP cores supportautomatic upgrade.The upgrade process renames

xy_real = ac – bd = ac – bd + (ad – bc) – (ad – bc) = (ac – ad + bc – bd) + (ad – bc) = ((a + b)(c – d)) + (ad –

Resource Utilization and PerformanceThe following table provides resource utilization and performance information for theALTMULT_COMPLEX megafunction.

parameter representation_a = "SIGNED",parameter representation_b = "SIGNED",parameter width_a = 1,parameter width_b = 1,parameter

ALTMULT_COMPLEX PortsTable 10-2: ALTMULT_COMPLEX IP Core Input PortsPort Name Required Descriptionaclr No Asynchronous clear for the complex multiplie

Table 10-4: ALTMULT_COMPLEX Megafunction ParametersParameter Name Type Required DescriptionIMPLEMENTATION_STYLE String Yes Specifies the representatio

Parameter Name Type Required DescriptionWIDTH_B Integer Yes Specifies the width of the datab_real[] and datab_imag[] ports. Valuemust be 256 bits or l

The following settings are observed in this example:• The widths of the data inputs are all set to 8 bits• The widths of the output ports are set to 1

ALTSQRT (Integer Square Root)112014.12.19UG-01063SubscribeSend FeedbackThe ALTSQRT megafunction implements a square root function that calculates the

Device familyInput datawidthOutputlatencyLogic UsagefMAX (MHz) (8)AdaptiveLook-UpTable (ALUT)DedicatedLogicRegister(DLR)AdaptiveLogicModule(ALM)Strati

clk:in std_logic := '1';ena:in std_logic := '1';q:out std_logic_vector(Q_PORT_WIDTH-1 downto 0);radical:in std_logic_vector(WIDTH-

Figure 1-7: Upgrading IP CoresDisplays upgrade status for all IP coresin the ProjectUpgrades all IP core that support “Auto Upgrade”Upgrades individua

Parameter Name Type Required DescriptionR_PORT_WIDTH Integer Yes Specifies the width of the remainder[] output port.PIPELINE Integer No Specifies the

PARALLEL_ADD (Parallel Adder)122014.12.19UG-01063SubscribeSend FeedbackThe PARALLEL_ADD megafunction performs add or subtract operations on a selected

Table 12-1: PARALLEL_ADD Resource Utilization and PerformanceDevice familyInput datawidthOutputlatencyLogic UsagefMAX (MHz) (9)AdaptiveLook-UpTable (A

The VHDL component declaration is located in the VHDL Design File (.vhd)altera_mf_components.vhd in the <Quartus II installation directory>\libr

ParametersThe following table lists the parameters for the PARALLEL_ADD megafunction.Table 12-4: PARALLEL_ADD Megafunction ParametersParameter Name Ty

This design example uses the LPM_MULT and PARALLEL_ADD megafunctions to generate a shiftaccumulator. This function implements the shift-and-accumulate

Document Revision History132014.12.19UG-01063SubscribeSend FeedbackThe following table lists the revision history for this document.Table 13-1: Docume

Date Version ChangesFebruary 2013 3.1• Updated Table 52 on page 63 to include Stratix V informationfor accum_sload port.• Updated Table 54 on page 65

Related InformationAltera IP Release NotesMigrating IP Cores to a Different DeviceIP migration allows you to target the latest device families with IP

Simulating Altera IP Cores in other EDA ToolsThe Quartus II software supports RTL and gate-level design simulation of Altera IP cores in supportedEDA

Related InformationSimulating Altera DesignsUG-010632014.12.19Simulating Altera IP Cores in other EDA Tools1-13Integer Arithmetic MegafunctionsAltera

LPM_COUNTER (Counter)22014.12.19UG-01063SubscribeSend FeedbackThe LPM_COUNTER megafunction is a binary counter that creates up counters, down counters

ContentsInteger Arithmetic Megafunctions... 1-1Design Example Files...

Resource Utilization and PerformanceThe following table provides resource utilization and performance information for the LPM_COUNTERmegafunction.Tabl

output cout;output [15:0] eq;input cin;input [lpm_width-1:0] data;input clock, clk_en, cnt_en, updown;input aset, aclr, aload;input sset, sclr, s

Port Name Required Descriptioncnt_en No Count enable input to disable the count when asserted lowwithout affecting sload, sset, or sclr. If omitted, t

Port Name Required Descriptioneq[15..0] No Counter decode output. The eq[15..0] port is not accessibleusing the MegaWizard Plug-In Manager as it is fo

Parameter Name Type Required DescriptionLPM_HINT String NoWhen you instantiate a library ofparameterized modules (LPM) function in aVHDL Design File (

Parameter Name Type Required DescriptionLPM_PORT_UPDOWN String No Specifies the usage of the updown input port.If omitted the default value is PORT_CO

LPM_DIVIDE (Divider)32014.12.19UG-01063SubscribeSend FeedbackThe LPM_DIVIDE megafunction implements a divider to divide a numerator input value by ade

Table 3-1: LPM_DIVIDE Resource Utilization and PerformanceDevice familyInput datawidthOutputlatencyLogic UsagefMAX (MHz)AdaptiveLook-UpTable (ALUT)Ded

DENOM : in std_logic_vector(LPM_WIDTHD-1 downto 0);ACLR : in std_logic := '0';CLOCK : in std_logic := '0';CLKEN : in std_logic :=

The following table lists the parameters for the LPM_DIVIDE megafunction.Parameter Name Type Required DescriptionLPM_WIDTHN Integer Yes Specifies the

ALTECC (Error Correction Code: Encoder/Decoder)...5-1ALTECC_ENCODER Features...

Parameter Name Type Required DescriptionLPM_REMAINDERPOSITIVE String No Altera-specific parameter. You mustuse the LPM_HINT parameter to specifythe LP

Parameter Name Type Required DescriptionINTENDED_DEVICE_FAMILY String No This parameter is used for modelingand behavioral simulation purposes.Create

LPM_MULT (Multiplier)42014.12.19UG-01063SubscribeSend FeedbackThe LPM_MULT megafunction implements a multiplier to multiply two input data values to p

The LPM_MULT megafunction can be implemented using either logic resources or dedicated multipliercircuitry in Altera devices. Typically, the LPM_MULT

input [lpm_widths-1:0] sum;output [lpm_widthp-1:0] result;endmoduleVHDL Component DeclarationThe VHDL component declaration is located in the VHDL De

Port Name Required Descriptionaclr No Asynchronous clear port used at any time to reset thepipeline to all 0s, asynchronously to the clock signal. The

Parameter Name Type Required DescriptionINPUT_A_IS_CONSTANT String No You must use the LPM_HINT parameter tospecify the INPUT_A_IS_CONSTANTparameter i

Parameter Name Type Required DescriptionMAXIMIZE_SPEED Integer No Altera-specific parameter. You must usethe LPM_HINT parameter to specify theMAXIMIZE

Parameter Name Type Required DescriptionDSP_BLOCK_BALANCING String No Specifies whether to use a dedicatedmultiplier circuitry implementation.Values a

ALTECC (Error Correction Code: Encoder/Decoder)52014.12.19UG-01063SubscribeSend FeedbackThe error correction code (ECC) is a error detection and corre

Verilog HDL Prototype...8-

Figure 5-1: ALTECC_ENCODER Portsdata[]instALTECC_ENCODERclockenclockq[]aclrFigure 5-2: ALTECC_DECODER Portsdata[]instALTECC_DECODERclockenclockq[]aclr

Data Width Number of Parity Bits Total Bits (Code Word)27-57 6+1 34-6458-64 7+1 66-72The parity bit derivation uses an even-parity checking. The addit

Table 5-2: ALTECC Resource Utilization and Performance for Stratix III DevicesConfigurationInputdatawidthOutputlatencyLogic UsagefMAX (MHz) AdaptiveLo

ConfigurationInputdatawidthOutputlatencyLogic UsagefMAX (MHz)AdaptiveLook-UpTable(ALUT)DedicatedLogicRegister(DLR)AdaptiveLogic Module(ALM)ALTECC_ENCO

The following Verilog HDL prototype is located in the Verilog Design File (.v) lpm.v in the <Quartus IIinstallation directory>\eda\synthesis dir

data:in std_logic_vector(width_codeword-1 downto 0);q:out std_logic_vector(width_dataword-1 downto 0));end component;VHDL LIBRARY_USE DeclarationThe V

Port Name Required Descriptionclock Yes Clock input port that provides the clock signal to synchronize theencoding operation. The clock port is requir

The following table lists the parameters for the ALTECC_DECODER megafunction.Table 5-8: ALTECC_DECODER Megafunction ParametersParameter Name Type Requ

Figure 5-4: Design Example 1: Simulation Waveform for the ECC Encoder5-10Understanding the Simulation ResultsUG-010632014.12.19Altera CorporationALTEC

The following sequence corresponds with the numbered items in the figure:• Data F0 is fed to the ECC encoder. As pipelining is enabled to have an outp

Design Example: 9-bit Square Root...11-4Understa

• The encoded input data for F0 is 14F0 (1 0100 1111 0000 in binary), as seen on the output port, q[], at17.5 ns.Design Example 1: Calculation of Pari

Table 5-12: Design Example 2: Arrangement of Parity Bits and Data Bits in Code Word 14F0MSB LSBP5* P4 P3 P2 P1 D7 D6 D5 D4 D3 D2 D1 D01 0 1 0 0 1 1 1

• All bits have their bit positions, and bit positions that are powers of 2 are used as parity bits(positions 1, 2, 4, 8 …). Table 38 lists the bit po

is needed on the retrieved data F0 (D8D7D6D5D4D3D2D1=1111 0000) based on the generatedsyndrome code. Therefore, the flag signals err_detected, err_cor

ALTERA_MULT_ADD (Multiply-Adder)62014.12.19UG-01063SubscribeSend FeedbackThe ALTERA_MULT_ADD megafunction allows you to implement a multiplier-adder.T

For Stratix V devices, the multiplier blocks and adder/accumulator block is combined in a single MACblock.The multipliers and adders of the ALTERA_MUL

• Provides an option to dynamically switch between add and subtract operation• Supports optional asynchronous clear and clock enable input ports• Supp

The following shows the pre-adder coefficient mode of a multiplier.Figure 6-3: Pre-adder Coefficient Modea0b0Mult0resultcoef+/-Preaddercoefsel0Pre-add

The following settings are applied in this mode:• The width of the dataa[] input (WIDTH_A) must be less than or equals to 17 bits• The width of the da

Figure 6-6: Pre-adder Constant Modea0Mult0resultcoefcoefsel0Systolic Delay RegisterIn a systolic architecture, the input data is fed into a cascade of

Integer Arithmetic Megafunctions12014.12.19UG-01063SubscribeSend FeedbackYou can use Altera® integer megafunction IP cores to perform mathematical ope

N represents the number of cycles of data that has entered into the accumulator, y(t) represents the outputat time t, A(t) represents the input at tim

Figure 6-9: Systolic Delay Register Implementation of 4 Multipliersa0b0Mult0resultchaininchainina1b1Mult1a2b2Mult2a3b3Mult3result+/-+/-+/-+/-Systolic

The following lists the advantages of systolic register implementation:• Reduces DSP resource usage• Enables efficient mapping in the DSP block using

The following figure shows the double accumulator implementation.Figure 6-12: Double Accumulatora0b0a1b1Mult0Mult1Accumulator feedba ckOutput result+

Port name Required Descriptiondatab [] Yes Data input to the multiplier. Input port [NUMBER_OF_MULTIPLIERS * WIDTH_B - 1 … 0] widedatac [] No Data inp

Table 6-2: ALTERA_MULT_ADD MegaFunction Output PortsPort Name Required Descriptionresult [] Yes Multiplier output port. Output port [WIDTH_RESULT - 1

Parameter Name Type Required DescriptionINPUT_SOURCE_A[0…3] String No Specifies the data source to the firstmultiplier. Values are DATAA and SCANA. If

Parameter Name Type Required DescriptionSIGNED_ACLR_[] String No Parameter [A, B]. Specifies the asynchro‐nous clear signal for the first register on

Parameter Name Type Required DescriptionADDNSUB_MULTIPLIER_REGISTER[] String No Parameter [1, 3]. Specifies the clock signalfor the register on the co

Parameter Name Type Required DescriptionINPUT_REGISTER_C[0…3] String No Specifies the clock port for the datac[]operand of the multiplier. Values areU

Altera also provides floating-point IP cores. For more information about the floating-point IP cores, referto the Floating-Point IP Cores User Guide.D

Parameter Name Type Required DescriptionSYSTOLIC_DELAY3 String No Specifies the clock source for the systolicregister inputs of the third multiplier.

Parameter Name Type Required DescriptionINPUT_B[0 … 3]_LATENCY_CLOCK String No Specifies the clock signal for the pipelineregister on the correspondin

Parameter Name Type Required DescriptionADDNSUB_MULTIPLIER_LATENCY_ACLR[]String No Parameter [1, 3]. Specifies the asynchro‐nous clear signal for the

altmult_add_ex_msim (ModelSim-Altera files)Understanding the Simulation ResultsThe following settings are observed in this example:• The widths of the

ALTMEMMULT (Memory-based ConstantCoefficient Multiplier)72014.12.19UG-01063SubscribeSend FeedbackThe ALTMEMMULT megafunction is used to create memory-

Resource Utilization and PerformanceThe following table provides resource utilization and performance information for the ALTMEMMULTmegafunction.Table

input wire sclr,input wire [width_s-1:0] sel,input wire sload_coeff,input wire sload_data)/* synthesis syn_black_box=1 */;endmoduleVHDL Component Decl

Port Name Required Descriptionsel[] No Fixed coefficient selection. The size of the input port depends on theWIDTH_S parameter value.sload_coeff No Sy

Parameter Name Type Required DescriptionDATA_REPRESENTATION String No Specifies whether the coeff_in[]input port and the pre-loadedcoefficients are si

Understanding the Simulation ResultsThe following settings are observed in this example:• The data_in[] and coeff_in[] input widths are both set to 8

IP Catalog and Parameter EditorThe Quartus II IP Catalog (Tools > IP Catalog) and parameter editor help you easily customize andintegrate IP cores

Figure 7-3: Multiplication with Coefficient of 2The following sequence corresponds with the numbered items in the figure:1. The following sequence cor

Figure 7-4: Multiplication with Coefficient of 3The following sequence corresponds with the numbered items in the figure:1. At 190 ns, the sload_coeff

ALTMULT_ACCUM (Multiply-Accumulate)82014.12.19UG-01063SubscribeSend FeedbackThe ALTMULT_ACCUM megafunction allows you to implement a multiplier-adder.

A multiplier-accumulator accepts a pair of inputs, multiplies the two inputs together, and feeds theirresult into an accumulator to be added to or sub

Table 8-1: ALTMULT_ACCUM Resource Utilization and PerformanceDevice familyInput datawidthNumber ofmultipliersLogic Usage18-bit DSP fMAX (MHz) (5)Adapt

Verilog HDL PrototypeTo view the Verilog HDL prototype for the megafunction, refer to the Verilog Design File (.v) altera_mf.vin the <Quartus II in

Port Name Required Descriptionaclr2 No The third asynchronous clear input. The aclr2 port is activehigh.aclr3 No The fourth asynchronous clear input.

Port Name Required Descriptionresult[] Yes Accumulator output port. The size of the output port dependson the WIDTH_RESULT parameter value.scanouta[]

Parameter Name Type Required DescriptionACCUM_SLOAD_PIPELINE_ACLR String No Specifies the asynchronousclear signal for the secondregister on the accum

Parameter Name Type Required DescriptionADDNSUB_PIPELINE_REG String No Specifies the clock for thesecond register on theaddnsub port. Values areUNREGI

Note: The IP Catalog is also available in Qsys (View > IP Catalog). The Qsys IP Catalog includesexclusive system interconnect, video and image proc

Parameter Name Type Required DescriptionINPUT_ACLR_B String No Specifies the asynchronousclear port for the datab[]port. Values are ACLR0,ACLR1, ACLR2

Parameter Name Type Required DescriptionMULTIPLIER_ACLR String No Specifies the asynchronousclear signal for the registerimmediately following themult

Parameter Name Type Required DescriptionPORT_SIGNB String No Specifies the usage of thesignb input port. Values arePORT_USED, PORT_UNUSED,and PORT_CON

Parameter Name Type Required DescriptionSIGN_PIPELINE_REG_[] String No Parameter [A,B]. Specifiesthe clock signal for thesecond register on thecorresp

Table 8-7: ALTMULT_ACCUM Megafunction Parameters (Arria V, Cyclone V, and Stratix V Devices Only)Parameter Name Type Required DescriptionINPUT_ACLR_C0

Parameter Name Type Required DescriptionINPUT_REGISTER_C0 String No Specifies the clock port forthe datac[] operand of thefirst multiplier. Values are

Parameter Name Type Required DescriptionMUTIPLIER3_DIRECTION String No Specifies whether the fourthand all subsequent odd-numbered multipliers add ors

Parameter Name Type Required DescriptionPREADDER_DIRECTION_3 String No Specifies whether the pre-adder of the fourth andcorresponding multiplieradds o

Parameter Name Type Required DescriptionCOEFFSEL_A_ACLR String No Specifies the asynchronousclear source for thecoefficient inputs to the firstmultipl

Parameter Name Type Required DescriptionSYSTOLIC_DELAY1 String No Specifies the clock source forthe systolic register inputs ofthe first multiplier. V