Altera LVDS SERDES Transmitter / Receiver Instrukcja Użytkownika

LVDS SERDES Transmitter/Receiver IP Cores UserGuide2014.12.15UG-MF9504SubscribeSend FeedbackThe low-voltage differential signaling serializer or deser

• To upgrade a single IP core that supports auto-upgrade, type the following command:quartus_sh –ip_upgrade –variation_files <my_ip_filepath/my_ip&

Table 5: ALTLVDS_TX Parameter SettingsOption DescriptionGeneral (page 3)Implement Deserializer circuitry inlogic cellsTurn on this option to implement

Option DescriptionUse External PLLTurn on this option to use an external PLL to clock theSERDES transmitter. When you turn on this option, theoptions

Option DescriptionUse 'tx_pll_enable' input portTurn on to control the enable port of the fast PLL that the IPcore uses with this function.I

Option DescriptionRegister 'tx_in' input port usingTurn on this option to specify whether input registers areclocked by the tx_inclock signa

Option DescriptionWhat is the outclock divide factor (B)? Specifies the frequency of the tx_outclock signal as thetransmitter output data rate divided

Option DescriptionWhat is the clock resource used for 'tx_coreclock'?Specifies the clock resource type fed to the tx_coreclocksignal. Allowe

Table 6: ALTLVDS_RX Parameter SettingsOption DescriptionGeneral (page 3)Implement Deserializer circuitry inlogic cellsTurn on this option to implement

Option DescriptionWhat is the deserialization factor?Determines the number of serial input data bits that thereceiver deserializes and sends to the co

Option DescriptionUse shared PLL(s) for receivers andtransmittersWhen you turn on this option, your LVDS receivers andtransmitters can share the same

Features Supported devicesSoft clock data recovery (CDR) modesupportAll Arria and Stratix(2) series devices.Note: Altera recommends implementing the B

Option DescriptionUse source-synchronous mode of thePLLTurn on this option to ensure that the IP core instance makesthe required phase adjustment to g

Option DescriptionUse 'rx_dpll_enable' input portEnables the path through the DPA circuitry. The optionsupports dynamic, channel-by-channel

Option DescriptionUse 'rx_dpa_locked' output portThe DPA block samples the data on one of eight phase clockswith a 45° resolution between ph

Option DescriptionEnable PLL CalibrationTurn on this option to phase-shift the PLL outputs when thedpa_pll_cal_busy signal is high. The default settin

Option DescriptionAlign data to the rising edge of clock When you turn on this option, the data path is registered onthe positive edge of the diffiocl

Option DescriptionEnable independent bitslip controls foreach channelTurn on this option to allow an independent rx_data_alignsignal for each channel

Related Information• Introduction to Altera IP Cores• Stratix IV Device Family Errata SheetCommand Line Interface ParametersExpert users can choose to

Parameter Type Descriptiondeserialization_factor IntegerSpecifies the number of bits per channel.The following is the device support and its valueswit

Parameter Type Descriptioninclock_data_alignment StringSpecifies the phase alignment of the tx_in[] and tx_inclock input ports in terms of the tx_incl

Parameter Type Descriptionoutclock_alignment StringSpecifies the alignment of tx_outclock with respectto the VCO of a fast PLL. The clock phase alignm

For the Stratix series, the side I/O banks contain dedicated SERDES circuitry, which includes the PLLs,serial shift registers, and parallel registers.

Parameter Type Descriptionoutclock_duty_cycle IntegerSpecifies the external clock timing constraints. Avalue of 50 is not supported in the outclock_du

Parameter Type Descriptionoutput_data_rate IntegerSpecifies the data rate out of the PLL. The multiplica‐tion value for the PLL is OUTPUT_DATA_RATE/IN

Parameter Type Descriptionuse_no_phase_shift String When set to OFF, a phase shift of 90° is added to theclock to center the clock in the data. Use th

Devices DESERIALIZATION_FACTORValueOUTCLOCK_DIVIDE_BY ValueCyclone, Cyclone II,Cyclone III, Cyclone IV,and Cyclone V4248525106261272714824816929181024

Table 9: ALTLVDS_RX ParametersParameter Type Descriptionbuffer_implementation StringSpecifies where to implement the buffer. Thevalues are MUX, RAM, a

Parameter Type Descriptiondeserialization_factor IntegerSpecifies the number of bits per channel.The values of this parameter for each supporteddevice

Parameter Type Descriptionenable_dpa_fifo String Indicates whether the DPA FIFO buffer isenabled for this channel.You must enable therx_dpa_locked por

Parameter Type Descriptioninclock_data_alignment StringSpecifies the phase alignment of the rx_in andrx_inclock input ports in terms of the rx_inclock

Parameter Type Descriptionpll_self_reset_on_loss_lock String The values are ON and OFF. If omitted, thedefault value is OFF. When this parameter isena

Parameter Type Descriptionreset_fifo_at_first_lock String Specifies when the bit-serial FIFO resets.Normally, the bit-serial FIFO is reset when theDPA

performance. After you purchase a license, visit the Self Service Licensing Center to obtain a licensenumber for any Altera product.Figure 1: IP Core

PortsThis section describes the ports for the ALTLVDS_TX and ALTLVDS_RX IP cores.ALTLVDS_TX PortsThe following table lists the input and output ports

Port Name Direction Width (Bit) Descriptiontx_inclockInput 1Reference clock input for the transmitter PLL.The parameter editor automatically selects t

Related Information• Introduction to Altera IP Cores• PLL Clock Signals for LVDS Interface in External PLL Mode on page 62ALTLVDS_RX PortsThe followin

Port Name Direction Width (Bit) Descriptionrx_data_align_reset Input 1 Resets the byte alignment circuitry. Use therx_data_align_reset input port when

Port Name Direction Width (Bit) Descriptionrx_in[] Input n LVDS serial data input port of n channelswide. rx_in[(n-1)..0] is deserialized anddriven on

Port Name Direction Width (Bit) Descriptionrx_cda_max Output n Data re-alignment (bit slip) roll-over signal.When high for one parallel clock cycle, t

Related Information• Introduction to Altera IP Cores• PLL Clock Signals for LVDS Interface in External PLL Mode on page 62Prototypes and Component Dec

DPA ModeIn DPA mode, the DPA circuitry automatically chooses the best phase to compensate for the skewbetween the source-synchronous clock and the rec

Figure 7: ALTLVDS_RX Block in Standard ModeDPAALTLVDS_RX slow registersdivfwdclkCore capture & sync registersCore sync registers÷rx_out[]rx_d

Figure 8: ALTLVDS_RX Block in No Output Register ModeDPAALTLVDS_RX CoreALTLVDS_RX fast registersALTLVDS_RX slow registersdivfwdclk÷rx_out[]rx_divfwdc

Figure 2: Quartus II IP CatalogSearch and filter IP for your target deviceDouble-click to customize, right-click for informationNote: The IP Catalog i

Figure 9: DPA Misalignment IssueDPA takes much longer time than anticipated to lock to the optimum phase of 3Invalid Data *0123rx_resetValid Datarx_dp

1. The following events occur during the DPA calibration process:2. The ALTLVDS_RX IP core counts 256 data transitions, then inserts delay elements on

by-channel basis. If the PLL has not locked to a stable clock source, the DPA circuit might lock pre-maturely to a non-ideal phase tap. Use the rx_res

The word aligner or the bit-slip circuit can be reset using the rx_cda_reset port. This circuit can be resetanytime and is not dependent on the PLL or

Dedicated SERDESThe ALTLVDS_TX and ALTLVDS_RX IP cores implemented in a dedicated SERDES and using the DPAmode are characterized and guaranteed to fun

Where:• RSKM—is the timing margin between the receiver's clock input and the data input SW.• Time unit interval (TUI)—is the time period of the s

Figure 11: Differential High-Speed Timing Diagram and Timing Budget for Non-DPA ModeTUIRCCSRCCSSWRCCSRSKM RSKMSWRSKM RSKMExternalInput ClockInternalCl

For Stratix IV devices:RCCS = 100 ps (pending characterization)SW = 300 ps (pending characterization)TUI = 1000 psTotal RCCS = RCCS + Board channel-to

To obtain the TCCS report (report_TCCS), follow these steps:1. In the Quartus II software, under the Tools menu, click TimeQuest Timing Analyzer.2. Fr

a. Right-click on the synchronous input port and select Set Input Delay.b. The Set Input Delay dialog box appears.c. Select the desired clock using th

Figure 3: IP Parameter EditorsView IP portand parameter detailsApply preset parameters forspecific applicationsSpecify your IP variation nameand targe

set_input_delay -clock [get_clocks virtual_clock_lvds] -clock_fall -max 0.200 [get_ports rx_in*] -add_delayset_input_delay -clock [get_clocks virtual_

Port Name Constraint TypeOption DescriptionGUI Setting SDC commandRise, Fall, Both -clock fall-clock risesSpecifies the clock's risingand falling

The Recommended Trace Delay Addition column in the report panel displays the recommendedamount of trace delay that you must add to each trace of the c

From the PLL To the ALTLVDS Transmitter To the ALTLVDS ReceiverLoad enable output (c1) tx_enable (load enable to thetransmitter)rx_enable (load enable

Table 14: Example Settings to Generate Three Output Clocks using PLL IP CoreThis table shows an example with the parameter values that you can set in

Figure 15: Phase Relationship for External PLL Interface SignalsD1 D2 D3 D4 D5 D6 D7 D8D9 D10inclk0VCO clk (internal PLL clk)c0 (-180° phase shift)c1

You can use the functional simulation model and the testbench or example design generated with your IPcore for simulation. The functional simulation m

Generating ALTLVDS IP Core Using Clear Box GeneratorApart from the IP core parameter editor, you can also use the clear box generator, a command-linee

Date Version ChangesNovember 2014 2014.11.17• Restructured and updated sections that describe the external PLLmode and the relevant ALTPLL IP core par

Date Version ChangesJune 2013 2013.06.10• Removed Use clock pin parameter. This parameter is no longeravailable for the megafunction beginning from AC

7. To generate an HDL instantiation template that you can copy and paste into your text editor, clickGenerate > HDL Example.8. Click Finish. The pa

Date Version ChangesJune 2013 2013.06.10• Updated Standard Mode on page 47 to add a note to recommendusing rx_divfwdclk (instead of any static clock)

Date Version ChangesJune 2011 v.8.0• Reorganized the document format.• Added "Source-Synchronous Timing Analysis and TimingConstraints" sect

Date Version ChangesDecember 2008 v4.0 Updated for the Quartus II software 8.1:• Removed figures.• Added Stratix IV to Device Family Support.• Updated

Figure 5: IP Core Generated FilesNotes:1. If supported and enabled for your IP variation2. If functional simulation models are generated3. Ignore this

IP Core Status Corrective ActionUpgrade Unsupported Upgrade of the IP variation is not supported in the current version of theQuartus II software due