Altera Embedded Peripherals IP Instrukcja Użytkownika

Embedded Peripheral IP User GuideSubscribeSend FeedbackUG-010852014.24.07101 Innovation DriveSan Jose, CA 95134www.altera.com

Document Revision History...24-6Inte

Include: <altera_16550_uart.h>Parameters: context – device of the UARTReturns: noneDescription: Interrupt handler to process UART interrupts top

Figure 9-7:typedef enum stopbit {ONE =0,TWO } StopBit; typedef enum paritybit { ODD =0, EVEN, NOPARITY } ParityBit;typedef enum databit { CS_

Figure 9-8:typedef struct altera_16550_uart_state_s{ alt_dev dev; void* base; /* The base address of the device */

#include <unistd.h>#include <sys/time.h>#include <time.h>#include "system.h"#include "altera_16550_uart.h"#inclu

RXMessage[0], Match); } break; case 1: printf("Ping Pong Baud Rate Test: UART#1 to UART#

usleep(1000); if(ERROR== altera_16550_uart_read(uart_1, RXMessage, 1, 0)) return ERROR; if(TXMessage[0]

printf("Ping Pong FIFO Test: UART#1 to UART#0\n"); CharCounter=altera_16550_uart_write(uart_1, &TXMessage

SPI Core102014.24.07UG-01085SubscribeSend FeedbackCore OverviewSPI is an industry-standard serial protocol commonly used in embedded systems to connec

Figure 10-1: SPI Core Block Diagram (Master Mode)clockcontrol control baud rate divisor*IRQsclkmosimisoss_n0ss_n1ss_n15 *Not present on SP

from 8 to 32. After a master peripheral writes a value to the txdata register, the value is copied to the shiftregister and then transmitted when the

altera_avalon_mailbox_post()... 27-6Document Revisio

for each active edge of sclk. The SPI core divides the Avalon-MM system clock using a clock divider togenerate the sclk signal.When the SPI core is co

Figure 10-3: SPI Core in a Multi-Slave Environment SPIMasterDevice sclk mosi misoss_n0ss_01sclk mosi miso ss_n0 SPI component(configured as slave

The actual frequency achieved will not be greater than the specified target value.Specify DelayTurning on this option causes the SPI master to add a t

Figure 10-5: Clock Polarity = 0, Clock Phase = 0Figure 10-6: Clock Polarity = 0, Clock Phase = 1Figure 10-7: Clock Polarity = 1, Clock Phase = 0Figure

alt_avalon_spi_command()Prototype: int alt_avalon_spi_command(alt_u32 base, alt_u32 slave, alt_u32 write_length,

Register MapAn Avalon-MM master peripheral controls and communicates with the SPI core via the six 32-bitregisters, shown in below in the Register Map

As an example, assume that the SPI core is idle (that is, the txdata register and transmit shift register areempty), when a CPU writes a data value in

Most bits (IROE, ITOE, ITRDY, IRRDY, and IE) in the control register control interrupts for statusconditions represented in the status register. For e

Date andDocumentVersionChanges Made Summary of ChangesJuly 2010v10.0.0No change from previous release. —November2009v9.1.0Revised register width in tr

Optrex 16207 LCD Controller Core112014.24.07UG-01085SubscribeSend FeedbackCore OverviewThe Optrex 16207 LCD controller core with Avalon® Interface (LC

Software Programming Model...31-3Softwar

Figure 11-1: LCD Controller Block DiagramaddressdatacontrolDB0 .. DB7R/WRSEOptrex 16207LCD ModuleLCDControllerAvalon-MM slaveinterface toon-chip logic

Sequence MeaningCR (\r) Moves the cursor to the start of the currentline.LF (\n) Moves the cursor to the start of the line andmove it down one lin

Document Revision HistoryTable 11-2: Document Revision HistoryDate andDocumentVersionChanges Made Summary of ChangesJuly 2014v14.0.0-Removed mention o

PIO Core122014.24.07UG-01085SubscribeSend FeedbackCore OverviewThe parallel input/output (PIO) core with Avalon® interface provides a memory-mapped in

Figure 12-1: System Using Multiple PIO CoresSystem Interconnect FabricCPUPIO core(output only)Program and DataMemoryPIOcore (bidirectional)IRQ LEDsEdg

• Level-sensitive—The PIO core hardware can detect a high level. A NOT gate can be inserted external tothe core to provide negative sensitivity.• Edge

WidthThe width of the I/O ports can be set to any integer value between 1 and 32.DirectionYou can set the port direction to one of the options shown b

Edge Capture RegisterTurn on Synchronously capture to include the edge capture register, edgecapture, in the core. The edgecapture register allows the

Table 12-2: Register Map for the PIO CoreOffset Register Name R/W (n-1) ... 2 1 00 dataread access R Data value currently on PIO inputswrite access W

After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If thosePIO ports are connected to device pins

Overview...

Document Revision HistoryTable 12-3: Document Revision HistoryDate andDocumentVersionChanges Made Summary of ChangesJuly 2014v14.0.0-Removed mention o

Avalon-ST Serial Peripheral Interface Core132014.24.07UG-01085SubscribeSend FeedbackCore OverviewThe Avalon® Streaming (Avalon-ST) Serial Peripheral I

Feature PropertyChannel Not supported.Error Not used.Packet Not supported.For more information about Avalon-ST interfaces, refer to the Avalon Interfa

provided to remove false timing paths. The frequency of the SPI master’s clock must be equal to or lowerthan the frequency of the core’s clock.Limitat

Date andDocumentVersionChanges Made Summary of ChangesNovember2008v8.1.0Changed to 8-1/2 x 11 page size. No change to content. —May 2008v8.0.0Initial

PCI Lite Core142014.24.07UG-01085SubscribeSend FeedbackCore OverviewThe PCI Lite core is a protocol interface that translates PCI transactions to Aval

PCIDeviceModePCI Target PCI Master ALUTs (2) LogicRegisterM9K MemoryBlocksI/O PinsMax (1) Enabled Enabled 1,347 876 5 50Table 14-1 :1. Min = One BAR w

Figure 14-1: Generic PCI-Avalon Bridge Block DiagramPCI Lite CoreControl RegisterAccess Avalon SlaveControlStatus RegistersPCI PrefetchableBridgeLogic

This Avalon-MM master port is optimized for low latency access from PCI-to-Avalon-MM slaves. This isoptimal for providing PCI target access to simple

Table 14-3: Avalon-to-PCI Address Translation Table – Address Range: 0x1000-0x1FFFAddress Bit Name AccessModeDescription0x10001:0 A2P_ADDR_SPACE0 W Ad

Introduction12014.24.07UG-01085SubscribeSend FeedbackThis user guide describes the IP cores provided by Altera that are included in the Quartus® II de

All PCI read transactions are completed as delayed reads. However, only one delayed read is accepted andprocessed at a time.PCI-to-Avalon Address Tran

Each entry in the address translation table also has two address space indication bits, which specify thetype of address space being mapped. If the ty

Avalon-To-PCI Read and Write OperationThe PCI Bus Access Slave port is a burst-capable slave that attempts to create PCI bursts that match thebursts r

Termination condition Resulting ActionAvalon-to-PCI command/writedata buffer running out of dataNormal master-initiated termination on the PCI bus.Mas

• PMW—Posted memory write.• DRR—Delayed read request.• DWR—Delayed write request. DWRs are I/O or configuration write operation requests. The PCI-Aval

Parameters Legal Values DescriptionSize of Address Pages 12–27 The supported address size (in bits) that can beassigned to each map number entries.Pre

Parameters Legal Values DescriptionClass Code <register value> Class code register. This parameter is a 24-bit hexadec‐imal value that sets the

#---------------- Do NOT change ------------------------------- ---- Change ----- array set map_user_pin_name_to_internal_pin_name {ad

The PCI testbench includes the following features:• Easy to use simulation environment for any standard Verilog HDL simulator• Open source Verilog HDL

USER COMMANDS SectionThe master transactor USER COMMANDS section contains the commands that initiate the PCI transac‐tions you want to run for your te

• PCI Lite Core• Mailbox CoreAltera recommends that you do not use these cores in new designs.For more information about Altera’s current IP offering,

1. Set the initialization parameters, which are defined in the master transactor model source code.These parameters control the address space reserved

MDIO Core152014.24.07UG-01085SubscribeSend FeedbackThe Altera Management Data Input/Output (MDIO) IP core is a two-wire standard managementinterface t

MDIO Frame Format (Clause 45)The MDIO core communicates with the external PHY device using frames. A complete frame is 64 bitslong and consists of 32-

FieldNameDescriptionREGAD/DataThe register address (REGAD) or data field is 16 bits. For an address cycle, it contains theaddress of the register to b

1. Issue a write to the device register at address offset 0x21 to configure the device, port, and registeraddresses of the PHY.2. Issue a read to the

AddressOffsetBit(s) Name AccessModeDescriptionTable 15-3 :1. The byte address for this register is 0x84.2. The byte address for this register is 0x80.

On-Chip FIFO Memory Core162014.24.07UG-01085SubscribeSend FeedbackCore OverviewThe on-chip FIFO memory core buffers data and provides flow control in

If Allow backpressure is turned on, the waitrequest signal is asserted whenever the data_in master triesto write to a full FIFO buffer. waitrequest is

per symbol, symbols per beat, and the width of the channel and error signals. The FIFO core performsthe endian conversion to conform to the output int

Offset Bits Field Description10 SOP The value of the startofpacket signal.1 EOP The value of the endofpacket signal.6:2 EMPTY The value of the empty s

Date andDocumentVersionChanges Made Summary of ChangesDecember2010v10.1.0Initial release. —UG-010852014.24.07Document Revision History1-3IntroductionA

is exactly the same as for the Avalon-MM to Avalon-ST FIFO core. See the for Memory Map table formore information.Figure 16-4: FIFO with Avalon-ST Inp

FIFO SettingsThe following sections outline the settings that pertain to the FIFO core as a whole.DepthDepth indicates the depth of the FIFO buffer, i

Avalon-ST Port SettingsThe following parameters allow you to specify the size and error handling of the Avalon-ST port or ports:• Bits per symbol• Sym

Function Name Descriptionaltera_avalon_fifo_read_ienable() Returns the value of the specified bit of theinterrupt enable register. To read all of the

base + 5 almostemptyThe table below outlines the use of the various fields of theTable 16-4: FIFO Status Field DescriptionsField Type Descriptionfill_

Bit(s) Name Description5 UNDERFLOW Is set to 1 for 1 cycle every time the FIFO underflows. The FIFOunderflows when an Avalon read master reads from an

Macros to access all of the registers are defined in altera_avalon_fifo_regs.h. For example, this fileincludes the following macros to access the stat

void* input_fifo_wrclk_irq_event_ptr = (void*) &input_fifo_wrclk_irq_event;/* Enable all interrupts. *//* Clear event register, set enable all irq

Parameters: address—the base address of the FIFO control slavemask—masks the read value from the status registerReturns: Returns the masked bits of th

Description: Gets the value of the almostempty register.altera_avalon_fifo_read_event()Prototype: int altera_avalon_fifo_read_event(alt_u32 address, a

SDRAM Controller Core22014.24.07UG-01085SubscribeSend FeedbackCore OverviewThe SDRAM controller core with Avalon® interface provides an Avalon Memory-

Returns: Returns 0 (ALTERA_AVALON_FIFO_OK) if successful, ALTERA_AVALON_FIFO_EVENT_CLEAR_ERROR if unsuccessful.Description: Clears the specified bits

Include: <altera_avalon_fifo_regs.h>, <altera_avalon_fifo_utils.h>Parameters: address—the base address of the FIFO control slavedata—the v

Returns: Returns 0 (ALTERA_AVALON_FIFO_OK) if successful, ALTERA_AVALON_FIFO_FULLif unsuccessful.Description: Writes the packet status information to

Document Revision HistoryTable 16-8: Document Revision HistoryDate andDocumentVersionChanges Made Summary of ChangesJuly 2014v14.0.0-Removed mention o

Avalon-ST Multi-Channel Shared Memory FIFOCore172014.24.07UG-01085SubscribeSend FeedbackCore OverviewThe Avalon® Streaming (Avalon-ST) Multi-Channel S

Table 17-1: Memory Utilization and Performance Data for Stratix II GX DevicesChannels ALUTsLogicRegistersMemory Blocks fMAX(MHz)M512 M4K M-RAM4 559 38

Functional DescriptionFigure 17-2: Avalon-ST Multi-Channel Shared Memory FIFO CoreAvalon-STStatus SourceAvalon-STStatus SourceMulti-Channel Shared FIF

Avalon-MM InterfacesThe core can have up to three Avalon-MM interfaces:• Avalon-MM control interface—Allows master peripherals to set and access almos

Parameter Legal Values DescriptionError width 0–32 The width of the error signal on the Avalon-ST datainterfaces.FIFO depth 2–232The depth of each mem

Parameter Legal Values DescriptionUse almost-fullthreshold 1—Turn on these parameters to implement the optionalAvalon-ST almost-full and almost-empty

Figure 2-1: SDRAM Controller with Avalon Interface Block DiagramAvalon-MM slaveinterfaceto on-chiplogicSDRAM Controller Coredata, controlAvalon-MM Sla

Control Register InterfaceTable 17-6: Control Interface Register MapByteOffsetName Access ResetValueDescription0 ALMOST_FULL_THRESHOLD RW 0 Primary al

Table 17-7: Fill-level Interface Register MapByteOffsetName Access ResetValueDescription0 fill_level_0 RO 0Fill level for each channel. Each register

SPI Slave/JTAG to Avalon Master Bridge Cores182014.24.07UG-01085SubscribeSend FeedbackCore OverviewThe SPI Slave to Avalon® Master Bridge and the JTAG

Figure 18-2: System with a JTAG to Avalon Master Bridge CoreaF tcennocretnI metsySbcirRest of the SystemHostPCAltera FPGAJTAG to Transaction Bridgesrc

When the transaction is complete, the bridges send a response to the host system using the same protocol.ParametersFor the SPI Slave to Avalon Master

Avalon-ST Bytes to Packets and Packets toBytes Converter Cores192014.24.07UG-01085SubscribeSend FeedbackThe Avalon® Streaming (Avalon-ST) Bytes to Pac

InterfacesTable 19-1: Properties of Avalon-ST InterfacesFeature PropertyBackpressure Ready latency = 0.Data Width Data width = 8 bits; Bits per symbol

Operation—Avalon-ST Packets to Bytes Converter CoreThe Avalon-ST Packets to Bytes Converter core receives packetized data and transforms the packets t

Avalon Packets to Transactions Converter Core202014.24.07UG-01085SubscribeSend FeedbackCore OverviewThe Avalon® Packets to Transactions Converter core

Feature PropertyData Width Data width = 8 bits; Bits per symbol = 8.Channel Not supported.Error Not used.Packet Supported.The Avalon-MM master interfa

standards, and therefore are capable of interfacing with a greater variety of SDRAM chips. For details,refer to the device handbook for the target dev

Table 20-3: Transaction SupportedTransactionCodeAvalon-MM Transaction Description0x00 Write, non-incrementingaddress.Writes data to the given address

Document Revision HistoryTable 20-4: Document Revision HistoryDate andDocumentVersionChanges Made Summary of ChangesJuly 2014v14.0.0-Removed mention o

Scatter-Gather DMA Controller Core212014.24.07UG-01085SubscribeSend FeedbackCore OverviewThe Scatter-Gather Direct Memory Access (SG-DMA) controller c

Figure 21-1: SG-DMA Controller Core with Streaming Peripheral and External MemoryAltera FPGA SOPC Builde r Syste mSSc atter Gather DMA Controller C

the estimated resource usage for a SG-DMA controller core used for memory to memory transfer. Thecore is configurable and the resource utilization var

Descriptor ProcessorThe descriptor processor reads descriptors from the descriptor list via its Avalon® Memory-Mapped(MM) read master port and pushes

Figure 21-3: Example of Memory-to-Memory ConfigurationMAva lon-MM Ma ste r P ortSAvalo n-MM S lave P ortAvalo n-ST So ur ce PortSRCAva lon-S T S in

Figure 21-5: Example of Stream-to-Memory ConfigurationSRCSRCMAvalon-MM Master PortSAvalon-MM S lave P ortAvalon-ST So urce PortAvalon-ST S ink P ort

• In memory-to-memory configurations, the DMA read block receives the source address from itscommand FIFO and starts reading data to fill the FIFO on

The list below describes how the error signals in the SG-DMA core are implemented in the folowingconfigurations:• Memory-to-memory configurationNo err

ContentsIntroduction... 1-1Tool Support...

Performance ConsiderationsUnder optimal conditions, the SDRAM controller core’s bandwidth approaches one word per clock cycle.However, because of the

ParametersTable 21-5: Configurable ParametersParameter Legal Values DescriptionTransfer mode Memory ToMemoryMemory ToStreamStream ToMemoryConfiguratio

Simulation ConsiderationsSignals for hardware simulation are automatically generated as part of the Nios II simulation processavailable in the Nios II

32-bitWordOffsetRegister Name ResetValueDescriptionbase +1version 1 Indicate the hardware version number. Onlybeing used by software driver for softwa

Bit Bit Name Access Description5 RUN R/W Set this bit to 1 to start the descriptor processorblock which subsequently initiates DMA transac‐tions. Prio

Altera recommends that you read the status register only after the RUN bit in the control register iscleared.Table 21-8: Status Register Bit MapBit Bi

Byte OffsetField Names31 2423 16 15 8 7 0base + 4 Reservedbase + 8 destinationbase +12Reservedbase +16next_desc_ptrbase +20Reservedbase +24Reserved

Table 21-11: DESC_CONTROL Bit MapBit (s) Field Name Access Description0 GENERATE_EOP W When this bit is set to 1,the DMA read block assertsthe EOP sig

Programming with SG-DMA ControllerThis section describes the device and descriptor data structures, and the application programminginterface (API) for

Table 21-14: Descriptor Data Structuretypedef struct {alt_u32 *read_addr;alt_u32 read_addr_pad;alt_u32 *write_addr;alt_u32 write_addr_pad;alt_u32 *nex

Name Descriptionalt_avalon_sgdma_register_callback() Associates a user-specific callback routine with theSG-DMA interrupt handler.alt_avalon_sgdma_sta

controller core easily by selecting the appropriate preset value. The following preset configurations aredefined:• Micron MT8LSDT1664HG module• Four S

Thread-safe: No.Available fromISR:Not recommended.Include: <altera_avalon_sgdma.h>, <altera_avalon_sgdma_descriptor.h>, <altera_avalon_

Description: This function constructs a single SG-DMA descriptor in the memory specifiedin alt_avalon_sgdma_descriptor *desc for an Avalon-MM to Avalo

Description: This function constructs a single SG-DMA descriptor in the memory specified inalt_avalon_sgdma_descriptor *desc for an Avalon-ST to Avalo

Parameters: *desc—a pointer to the descriptor being constructed.*next—a pointer to the “next” descriptor. This does not need to be a complete orfuncti

Parameters: *desc—a pointer to the constructed descriptor to examine.Returns: Returns 0 if the descriptor is error-free, not owned by hardware, or a p

Parameters: *dev—a pointer to the SG-DMA device structure.Returns: voidDescription: Starts the DMA engine and processes the descriptor pointed to in t

Document Revision HistoryTable 21-16: Revision HistoryDate andDocumentVersionChanges Made Summary of ChangesJuly 2014v14.0.0Updated Register Maps tabl

Altera Modular Scatter-Gather DMA222014.24.07UG-01085SubscribeSend FeedbackOverviewIn a processor subsystem, data transfers between two memory spaces

Figure 22-1: mSDGMA Module Configuration with support for Memory-Mapped Reads and Writes22-2Feature DescriptionUG-010852014.24.07Altera CorporationAlt

Figure 22-2: mSGDMA Module Configuration with Support for Memory-Mapped Streaming Reads tothe Avalon-ST data bus.UG-010852014.24.07Feature Description

Settings AllowedValuesDefaultValuesDescriptionInclude a functionalmemory model in thesystem testbenchOn, Off On When on, Qsys functional simulation mo

Figure 22-3: mSGDMA Module Configuration with Support for Avalon-ST Data Write Streaming to theMemory-Mapped Bus.Altera mSGDMA support 32-bit addressi

The following paragraphs describe the behavior of the component interfaces.Descriptor Slave PortThe descriptor slave port is write only and configurab

Parameter Name Description Allowable RangeMaximum Transfer Legth Maximum transfer length. With shorterlength width being configured, the fasterfrequen

mSGDMA DescriptorsThe descriptor slave port is 128 bits for standard descriptors and 256 bits for extended descriptors. Thetables below show acceptabl

Byte Lanes0xC Control[31:0]Table 22-2: Extended Descriptor FormatByte LanesOffset 3 2 1 00x0 Read Address[31:0]0x4 Write Address[31:0]0x8 Length[31:0]

program the length field with the largest possible value of 0xFFFFFFFF. This allows you to specify amaximum packet size for each descriptor that has p

The control field is available for both the standard and extended descriptor formats. This field can beprogrammed to configure parked descriptors, err

Bit Sub-Field Name Definition23:16 Transmit Error / ErrorIRQ EnableFor MM->ST transfers, this field isused to specify a transmit error.This field i

Bit Sub-Field Name Definition12 End on EOPEnd on end of packet allows the writemaster to continuously transfer dataduring ST->MM transfers withoutk

Byte Lanes0x18 N/A <reserved>10x1C N/A <reserved>1Status RegisterTable 22-5: Status Register Bit DefinitionBit Name Description31:10 <r

Settings AllowedValuesDefaultValueDescriptionWrite recoverytime (t_wr, Noauto precharge)— 14 ns Write recovery if explicit precharge commands areissue

Table 22-6: Control Register Bit DefinitionBit Name Description31:10 <reserved> N/A5 Stop Descriptors Setting this bit will stop the SGDMA dispa

The following list explains each of the fields:• Actual bytes transferred is used to determine how many bytes were transferred when the mSGDMAis confi

DMA Controller Core232014.24.07UG-01085SubscribeSend FeedbackCore OverviewThe direct memory access (DMA) controller core with Avalon® interface perfor

Figure 23-1: DMA Controller Block DiagramAvalon-MMSave PortAddr,data,controlIRQSeparateAvalon-MMMaster PortsRegister Filestatusreadaddresswriteaddress

length registered is programmed with 64 and the burst count port will be 16. If a 64-bit data width DMAis programmed for a doubleword transfer of 8 by

Transfer SizeThe parameter Width of the DMA Length Register specifies the minimum width of the DMA’s transac‐tion length register, which can be betwee

Software Programming ModelThis section describes the programming model for the DMA controller, including the register map andsoftware declarations to

Request MeaningTable 23-2 :1. These macro names changed in version 1.1 of the Nios II Embedded Design Suite (EDS). Theold names (ALT_DMA_TX_STREAM_ON,

Offset Register Name Read/Write 31 13 12 11 10 9 8 7 6 5 4 3 2 1 06 control RW (2) SOFTWARERESETQUADWORDDOUBLEWORDWCONRCONLEENWEENREENI_ENGO WORDHW

length RegisterThe length register specifies the number of bytes to be transferred from the read port to the write port.The length register is specifi

structured as a single, monolithic block of memory. For example, even for a system that combines twoSDRAM chips, the generic memory model is implement

BitNumberBit Name Read/Write/ClearDescription8 RCON RW Reads from a constant address. When RCON is 0, the readaddress increments after every data tran

Document Revision HistoryTable 23-6: Document Revision HistoryDate andDocumentVersionChanges Made Summary of ChangesJuly 2014v14.0.0-Removed mention o

Video Sync Generator and Pixel ConverterCores242014.24.07UG-01085SubscribeSend FeedbackCore OverviewThe video sync generator core accepts a continuous

Figure 24-2: Video Sync Generator Block Diagramclkresetdatareadyvalidsopeoprgb_outhdvddenVIDEO SYNC GENERATORYou can configure various aspects of the

Parameter Name DescriptionVertical Sync PulseLinesThe width of the v-sync pulse in number of lines.Vertical Front PorchLinesThe number of blanking lin

Signal Name Width (Bits) Direction Descriptionvalid 1 Input This signal is not used by the video sync generator corebecause the core always expects va

Figure 24-4: Horizontal Synchronization Timing—24 Bits DataWidth and 1 Beat Per Pixelclkhddenrgb_outRGBHorizontal synchronization pulseHorizontal blan

Signal Name Width (Bits) Direction Descriptionclk 1 InputNot in use.reset_n 1 InputAvalon-ST Signalsdata_in 32 Input Incoming pixel data. Contains fou

Date andDocumentVersionChanges Made Summary of ChangesDecember2010v10.1.0Removed the “Device Support”, “Instantiating the Corein SOPC Builder”, and “R

Interval Timer Core252014.24.07UG-01085SubscribeSend FeedbackCore OverviewThe Interval Timer core with Avalon® interface is an interval timer for Aval

The address, data, and control signals connect in parallel to the two chips. The chipselect bus (cs_n[1:0])determines which chip is selected. The resu

The intervanl timer core has two user-visible features:• The Avalon Memory-Mapped (Avalon-MM) interface that provides access to six 16-bit registers•

example, if the associated system clock has a frequency of 30 ns, and the specified Timeout Period valueis 1 µs, the true timeout period will be 1.020

Option DescriptionSystem reseton timeout(watchdog)When this option is on, the core’s Avalon-MM slave port includes the resetre-quest signal. This sign

this timer. The driver is interrupt-driven, and therefore must have its interrupt signal connected in thesystem hardware.The Nios II integrated develo

Table 25-3: Register Map—32-bit TimerOffset Name R/WDescription of Bits15 ... 4 3 2 1 00 status RW (1) RUN TO1 control RW (1) STOP START CONT ITO2 per

Table 25-5: status Register BitsBit Name R/W/C Description0 TO RC The TO (timeout) bit is set to 1 when the internal counter reaches zero.Once set by

period_n RegistersThe period_n registers together store the timeout period value. The internal counter is loaded with thevalue stored in these registe

Date andDocumentVersionChanges Made Summary of ChangesJuly 2010v10.0.0No change from previous release. —November2009v9.1.0Revised descriptions of regi

Mutex Core262014.24.07UG-01085SubscribeSend FeedbackCore OverviewMultiprocessor environments can use the mutex core with Avalon® interface to coordina

• When the VALUE field is 0x0000, the mutex is unlocked and available. Otherwise, the mutex is lockedand unavailable.• The mutex register is always re

• Timing parameters of the device and SDRAM I/O pins — I/O timing parameters vary based on devicefamily and speed grade.• Pin location on the device —

Function Name Descriptionaltera_avalon_mutex_trylock() Tries to lock the mutex. Returns immediately if it fails tolock the mutex.altera_avalon_mutex_l

altera_avalon_mutex_first_lock()Prototype: int altera_avalon_mutex_first_lock(alt_mutex_dev* dev)Thread-safe: Yes.Available fromISR:No.Include: <al

altera_avalon_mutex_trylock()Prototype: int altera_avalon_mutex_trylock(alt_mutex_dev* dev, alt_u32value)Thread-safe: Yes.Available fromISR:No.Include

Date andDocumentVersionChanges Made Summary of ChangesDecember2010v10.1.0Removed the “Device Support”, “Instantiating theCore in SOPC Builder”, and “R

Mailbox Core272014.24.07UG-01085SubscribeSend FeedbackMultiprocessor environments can use the mailbox core with Avalon® interface to send messages bet

The mailbox component contains two mutexes: One to ensure unique write access to shared memory andone to ensure unique read access from shared memory.

The mailbox software programming model has the following characteristics and assumes there aremultiple processors accessing a single mailbox core and

Table 27-3: Writing to and Reading from a Mailbox#include <stdio.h>#include "altera_avalon_mailbox.h"int main(){ alt_u32 message =

altera_avalon_mailbox_get()Prototype: alt_u32 altera_avalon_mailbox_get (alt_mailbox_dev* dev, int*err);Thread-safe: Yes.Available fromISR:No.Include:

altera_avalon_mailbox_post()Prototype: int altera_avalon_mailbox_post (alt_mailbox_dev* dev, alt_u32msg);Thread-safe: Yes.Available fromISR:No.Include

Figure 2-5: Calculating the Maximum SDRAM Clock LagFigure 2-6: Calculating the Maximum SDRAM Clock LeadExample CalculationThis section demonstrates a

Vectored Interrupt Controller Core282014.24.07UG-01085SubscribeSend FeedbackCore OverviewThe vectored interrupt controller (VIC) core serves the follo

• One optional Avalon-ST interface input interface to receive the Avalon-ST output in systems withdaisy-chained VICsThe Sample System Layout Figure be

Functional DescriptionFigure 28-2: VIC Block DiagramControl Status Registerscsr_access(Avalon-MM slavefrom processor)InterruptRequestBlockinterrupt_co

The interrupt_controller_out and interrupt_controller_in interfaces have identical Avalon-STformats so you can daisy chain VICs together in SOPC Build

This block contains the majority of the VIC CSRs. The CSRs are accessed via the Avalon-MM slaveinterface.Optional output from another VIC core can als

Daisy Chaining VIC CoresYou can create a system with more than 32 interrupts by daisy chaining multiple VIC cores together. Thisis done by connecting

Table 28-6: Control Status RegistersOffset Register Name Access ResetValueDescription0 – 31 INT_CONFIG<n> R/W 0 There are 32 interrupt configura

Offset Register Name Access ResetValueDescription36 INT_RAW_STATUS R 0 The interrupt raw status register. INT_RAW_STATUS shows the unmasked state of t

Offset Register Name Access ResetValueDescription43 VEC_TBL_ADDR R 0 The vector table address register. VEC_TBL_ADDRprovides the RHA for the IRQ value

Table 28-8: The VIC_CONFIG Register MapBits Field Name Access ResetValueDescription0:2 VEC_SIZE R/W 0 The vector size field. VEC_SIZE specifies the nu

Table 2-3: Timing Parameters for Micron MT48LC4M32B2 SDRAM DeviceParameter SymbolValue (ns) in -7 Speed GradeMin. Max.Access timefrom CLK(pos. edge)CL

ParametersGeneration-time parameters control the features present in the hardware.The table below lists anddescribes the parameters you can configure.

• altera_vic_regs.h—Defines the core’s register map, providing symbolic constants to access the low-levelhardware.• altera_vic_funnel.h, altera_vic_ir

Data StructureTable 28-11: Device Data Structure#define ALT_VIC_MAX_INTR_PORTS (32)typedef struct alt_vic_dev{void *base; /* Base address of VIC */alt

• alt_ic_isr_register ()• alt_ic_irq_enable()• alt_ic_irq_disable()• alt_ic_irq_enabled()These functions write to the register map to change the setti

alt_vic_sw_interrupt_clear()Prototype: int alt_vic_sw_interrupt_clear(alt_u32 ic_id, alt_u32 irq)Thread-safe: NoAvailablefrom ISR:Yes; if interrupt pr

Thread-safe: NoAvailablefrom ISR:NoInclude: altera_vic_irq.h, altera_vic_regs.hParameters: ic_id—the interrupt controller identification number asdefi

VIC BSP SettingsThe VIC driver scripts provide settings to the BSP. The number and naming of these settings depends onyour hardware system's conf

Descrip‐tion:Enables interrupt preemption (nesting) if a higher priorityinterrupt is asserted while a lower priority ISR is executing, andthat higher

Descrip‐tion:Enables interrupt preemption (nesting) if a higher priorityinterrupt is asserted while a lower priority ISR is executing, forall interrup

Descrip‐tion:Specifies the linker section that each VIC's generated vector tableand each interrupt funnel link to. The memory device that thespec

Parameter Symbol Value (ns)Maximum clock-to-output time tCO_MAX2.477Maximum hold time after clock tH_MAX–5.607Maximum setup time before clock tSU_MAX5

Destina‐tion file:system.hDescrip‐tion:Specifies the RRS for the interrupt connected to thecorresponding port. Legal values are 1 to the number of sha

Default Settings for RRS and RILThe default assignment of RRS and RIL values for each interrupt assumes interrupt port 0 on the VICinstance attached t

• Each component’s interrupt interface in your system should only be connected to one VIC instanceper processor.• The number of shadow register sets f

Date andDocumentVersionChanges Made Summary of ChangesNovember2009v9.1.0Initial release. —28-24Document Revision HistoryUG-010852014.24.07Altera Corpo

Avalon-ST JTAG Interface Core292014.24.07UG-01085SubscribeSend FeedbackFunctional DescriptionThe figure below shows a block diagram of the Avalon-ST J

Core BehaviorThe Avalon-ST JTAG Interface core is supported when used with the System Console; a Tcl console thatprovides access to IP cores instantia

For more information about the System Console and its commands, refer to Analyzing and DebuggingDesigns with the System Console in volume 3 of the Qua

Date andDocumentVersionChanges Made Summary of ChangesNovember2008v8.1.0Changed to 8-1/2 x 11 page size. No change to content. —May 2008v8.0.0Initial

System ID Core302014.24.07UG-01085SubscribeSend FeedbackCore OverviewThe system ID core with Avalon® interface is a simple read-only device that provi

ConfigurationThe id and timestamp register values are determined at system generation time based on theconfiguration of the Qsys system and the curren

Compact Flash Core... 4-1Core Overview...

Date andDocumentVersionChanges Made Summary of ChangesDecember2010v10.1.0Removed the “Device Support”, “Instantiating the Core inSOPC Builder”, and “R

Document Revision HistoryTable 30-2: Document Revision HistoryDate andDocumentVersionChanges Made Summary of ChangesJuly 2014v14.0.0-Removed mention o

Performance Counter Core312014.24.07UG-01085SubscribeSend FeedbackCore OverviewThe performance counter core with Avalon® interface enables relatively

The performance counter core can have up to seven section counters.Global CounterThe global counter controls all section counters. The section counter

Offset Register NameBit DescriptionRead Write31 ... 0 31 ... 1 0...4n + 0 T[n]losection n clock cycle counter [31:0] (1) 0 =STOP4n + 1 T[n

Software FilesAltera provides the following software files for Nios II systems. These files define the low-level access tothe hardware and provide con

Name (1) MeaningPERFORMANCE_COUNTER_SPAN Number of hardware registersPERFORMANCE_COUNTER_HOW_MANY_SECTIONSNumber of section countersTable 31-3 :1. Exa

Table 31-5: Example 2:--Performance Counter Report--Total Time: 2.07711 seconds (103855534 clock-cycles)+-----------------+--------+-----------+------

Returns: —Description: Macro PERF_RESET() stops and disables all counters, resetting them to 0.PERF_START_MEASURING()Prototype: PERF_START_MEASURING(p

Parameters: p—performance counter core base address.n—counter section number. Section counter numbers start at 1. Do not refer tocounter 0 in this mac

Parameters: perf_base—Performance counter core base address.clock_freq_hertz—Clock frequency.num_sections—The number of section counters to display. T

Tri-State SDRAM32014.24.07UG-01085SubscribeSend FeedbackThe SDRAM controller core with Avalon® interface provides an Avalon Memory-Mapped (Avalon-MM)i

Description: Function perf_get_section_time() reads the raw time for a given section.This is the time, in clock cycles, that the section has been runn

Document Revision HistoryTable 31-6: Document Revision HistoryDate andDocumentVersionChanges Made Summary of ChangesJuly 2014v14.0.0-Removed mention o

PLL Cores322014.24.07UG-01085SubscribeSend FeedbackCore OverviewThe PLL cores, Avalon ALTPLL and PLL, provide a means of accessing the dedicated on-ch

Functional DescriptionFigure 32-1: PLL Core Block DiagramStatusControlaresetpfdenapllenainclke1e0c1c0lockedPLL LockedAvalon-MMSlave InterfacePLL Reset

or control signals which are not mapped to registers are exported to the top-level module. For details,refer to the Instantiating the Avalon ALTPLL Co

For each advanced signal present on the ALTPLL megafunction, you can select one of the following accessmodes:• Export—Exports the signal to the top le

Hardware Simulation ConsiderationsThe HDL files generated by SOPC Builder for the PLL cores are suitable for both synthesis andsimulation. The PLL cor

Table 32-3: Status Register BitsBit Number Bit Name Value afterresetDescription0 locked(2)1 Connects to the locked signal onthe ALTPLL megafunction. T

Phase Reconfig Control RegisterEmbedded software can control the dynamic phase reconfiguration via the phase reconfig controlregister.Table 32-5: Phas

Document Revision HistoryTable 32-7: Document Revision HistoryDate andDocumentVersionChanges Made Summary of ChangesDecember2010v10.1.0Removed the “De

Block DiagramFigure 3-1: Tri-State SDRAM Block Diagram altera _sdram_controllerInit FSMRequest BufferAvalon-MM InterfaceSDRAM InterfaceMainFSMSignal G

Altera MSI to GIC Generator332014.24.07UG-01085SubscribeSend FeedbackOverviewIn the PCI subsystem, Message Signaled Interrupts (MSI) is a feature that

The Altera MSI-to-GIC Generator provides storage for the MSI system-specified data value. It alsogenerates level interrupt output when there is an unr

When a new message data is written into Altera MSI-to-GIC Generator module, the storage wordassociated Status bit is set automatically and a level int

Error RegisterThe Error register bit is set automatically only when the associated message data word location thatcontains the write entry, indicating

Altera SMBus Core InterfaceThis diagram depicts the top level interfaces for the Altera SMBus Core.Figure 33-2: Altera SMBus Core Top Level Interfaces

Signal Width Direction Descriptionwrite 1 Input Avalon-MM writecontrolwritedata 32 Input Avalon-MM write databusreaddata 32 Output Avalon-MM read data

Component InterfaceThe Altera MSI-to-GIC Generator component consists of two Avalon-MM Slave interfaces, CSR and Datastorage. The component also provi

The configuration parameters of the Altera MSI-to-GIC Generator TCL component are listed, below:Table 33-10: Component parametersParameter Name Descri

Parameter Name Description Default value Allowable rangeDATA_ENTRY_DEPTHThis parameter affectsthe depth of FIFOimplemented at eachdata word address. T

Altera Interrupt Latency Counter342014.24.07UG-01085SubscribeSend FeedbackOverviewA processor running a program can be instructed to divert from its o

Table 3-2: Configuration Timing ParametersParameter GUI Legal Values Default Values UnitsCAS latency cycles 1, 2, 3 3 CyclesInitialization refresh cyc

Figure 34-1: Usage model of Interrupt Latency CalculatorProcessorInterrupt Latency CalculatorPeripheral DataMaster IRQ Receiver CSRSlave

instance to have only five counters, then only addressess 0x0 to 0x4 return a valid value when you try toread from it. When the IP user tries to read

Counter Stop RegistersTable 34-4: Counter Stop RegistersField Name Counter Stop RegistersBit Location 31 0If the ILC is configured to support the puls

Interrupt DetectorThe interrupt detector can be customized to detect either signal edges or pulse using the Qsys interface.The interrupt detector gene

Parameter Name Description Default Value Allowable RangeINTR_TYPEValue 0: levelsensitive interruptinputValue 1: edge/pulseinterrupt input0 0,1IRQ_PORT

Implementation DetailsInterrupt Latency Counter ArchitectureFigure 34-2: Interrupt Latency Calculator ArchitectureThe interrupt latency calculator ope

IP CaveatsThere are limitations in the Altera interrupt latency which the user needs to be aware of. This limitationarises due to the nature of state

Table 3-4: Avalon-MM Slave Interface SignalsSignal Width Direction Descriptionavs_read1 Input Avalon-MM read control.Asserted to indicate a readtransf

Table 3-5: Tristate Conduit Master / SDRAM Interface SignalsSignal Width Direction Descriptiontcm_grant1 Input When asserted, indicates thata tristate

Signal Width Direction Descriptiontcm_request1 Output The meaning of tcm_request depends on thestate of the tcm_grantsignal, as the following rulesdic

Signal Width Direction Descriptionsdram_dq_oen1 Output SDRAM data bus input.Valid only when pin-sharingmode is enabled.sdram_dq sdram_data_widthInput/

Signal Width Direction Descriptionsdram_cke1 Output SDRAM Clock Enable. TheSDRAM controller does notsupport clock-disable modes.The SDRAM controllerpe

Avalon-MM Slave Interface and CSRThe host processor perform data read and write operation to the external SDRAM devices through theAvalon-MM interface

HAL System Library Support...7-5Software Files..

Document Revision HistoryTable 3-6: Document Revision HistoryDate andDocumentVersionChanges Made Summary of ChangesJuly 2014v14.0- Initial Release3-10

Compact Flash Core42014.24.07UG-01085SubscribeSend FeedbackCore OverviewThe CompactFlash core allows you to connect systems built on Osys to CompactFl

The CompactFlash core maps the Avalon-MM bus signals to the CompactFlash device with propertiming, thus allowing Avalon-MM master peripherals to direc

CompactFlash Interface SignalNamePin Type CompactFlash PinNumberdata[7] Input/Output 6data[8] Input/Output 47data[9] Input/Output 48data[10] Input/Out

• altera_avalon_cf_regs.h—The header file that defines the core's register maps.• altera_avalon_cf.h, altera_avalon_cf.c—The header and source co

Table 4-4: cfctl Register BitsBit Number Bit Name Read/Write Description0 DET RO Detect. This bit is set to 1 when the core detects aCompactFlash devi

Date andDocumentVersionChanges Made Summary of ChangesNovember2009v9.1.0No change from previous release. —March 2009v9.0.0No change from previous rele

Common Flash Interface Controller Core52014.24.07UG-01085SubscribeSend FeedbackCore OverviewThe common flash interface controller core with Avalon® in

Functional DescriptionThe figure below shows a block diagram of the CFI controller in a typical system configuration. TheAvalon Memory-Mapped (Avalon-

The options provided are not intended to cover the wide range of flash devices available in the market. Ifthe flash chip on your target board does not

Document Revision History...9-20SPI

HAL System Library SupportThe Altera-provided driver implements a HAL flash device driver that integrates into the HAL systemlibrary for Nios II syste

Date andDocumentVersionChanges Made Summary of ChangesNovember2009v9.1.0Revised description of the timing page settings. —March 2009v9.0.0No change fr

EPCS Serial Flash Controller Core62014.24.07UG-01085SubscribeSend FeedbackCore OverviewThe EPCS serial flash controller core with Avalon® interface al

Functional DescriptionAs shown below, the EPCS device's memory can be thought of as two separate regions:• FPGA configuration memory—FPGA configu

software, the EPCS serial flash controller core signals are routed automatically to the device pins for theEPCS device.You, however, have the option n

Offset(32-bit Word Address)Register Name R/WBit Description31:00x100 Read Data R0x101 Write Data W0x102 Status R/W0x103 Control R/W0x104 Reserved —0x1

The HAL API for programming flash, including C-code examples, is described in detail in the .Nios II Flash Programmer User GuideFor details about mana

Date andDocumentVersionChanges Made Summary of ChangesMay 2008v8.0.0Updated the boot rom size.Added additional steps to perform to connect outputpins

JTAG UART Core72014.24.07UG-01085SubscribeSend FeedbackCore OverviewThe JTAG UART core with Avalon® interface implements a method to communicate seria

Figure 7-1: JTAG UART Core Block DiagramAvalon-MM slaveinterfaceto on-chiplogicJTAG UART CoreRegistersJTAGHubInterfaceIRQBuilt-In Feature of Altera FP

Interrupt Behavior...12-7Softwar

Figure 7-2: Example System Using the JTAG UART CorePC InterfaceHost PCJTAGServerDownloadCableAlteraDownloDebuggerDebuggerCDebug DataPC InterfaceJTAGHo

Write FIFO SettingsThe write FIFO buffers data flowing from the Avalon interface to the host. The following settings areavailable:• Depth—The write FI

characters via a console, giving the appearance of a terminal session with the system executing inhardware. The following options are available:• Do n

For Nios II processor users, the HAL system library API provides complete access to the JTAG UARTcore's features. Nios II programs treat the JTAG

Table 7-2: Example: Transmitting Characters to a JTAG UART Core/* A simple program that recognizes the characters 't' and 'v' */#i

Driver Options: Fast vs. Small ImplementationsTo accommodate the requirements of different types of systems, the JTAG UART driver has two variants,a f

• altera_avalon_jtag_uart_regs.h—This file defines the core's register map, providing symbolic constantsto access the low-level hardware. The sym

Bit(s) Name Access Description[32:16]RAVAIL R The number of characters remaining in the read FIFO (afterthe current read).A read from the data registe

The JTAG UART core has two kinds of interrupts: write interrupts and read interrupts. The WE and REbits in the control register enable/disable the int

Date andDocumentVersionChanges Made Summary of ChangesNovember2008v8.1.0Changed to 8-1/2 x 11 page size. No change to content. —May 2008v8.0.0No chang

Document Revision History...15-5On-C

UART Core82014.24.07UG-01085SubscribeSend FeedbackCore OverviewThe UART core with Avalon® interface implements a method to communicate serial characte

Avalon-MM Slave Interface and RegistersThe UART core provides an Avalon-MM slave interface to the internal register file. The user interface tothe UAR

A master peripheral can monitor the receiver's status by reading the status register's read-ready (RRDY),receiver-overrun error (ROE), break

The baud rate value is used to calculate an appropriate clock divisor value to implement the desired baudrate. Baud rate and divisor values are relate

Setting Legal Values DescriptionParity None, Even,OddThis setting determines whether the UART core transmits characters withparity checking, and wheth

accept another character, and to read data only when the core has data available. The UART core can alsooptionally include the end-of-packet register.

speed, or roughly one character per 20 clock cycles. You can choose one of the following options for thesimulated transmitter baud rate:• Accelerated

Table 8-2: Example: Printing Characters to a UART Core as stdout#include <stdio.h>int main (){printf("Hello world.\n");return 0;}The f

Table 8-3: Example: Sending and Receiving Characters/* A simple program that recognizes the characters 't' and 'v' */#include <

The small driver is a polled implementation that waits for the UART hardware before sending andreceiving each character. There are two ways to enable

Document Revision History...17-8SPI

For details about the ioctl() function, refer to the Nios II Software Developer's Handbook.LimitationsThe HAL driver for the UART core does not s

Some registers and bits are optional. These registers and bits exists in hardware only if it was enabled atsystem generation time. Optional registers

Bit Name Access Description2 BRK RC Break detect. The receiver logic detects a break when the RXD pin is heldlow (logic 0) continuously for longer tha

Bit Name Access Description10 (1)DCTS RC Change in clear to send (CTS) signal. The DCTS bit is set to 1 whenever alogic-level transition is detected o

Bit Name Access Description3 IROE RW Enable interrupt for a receiver overrun error.4 ITOE RW Enable interrupt for a transmitter overrun error.5 ITMT R

The endofpacket register is an optional hardware feature. If the Include end-of-packet registerhardware option is not enabled, the endofpacket registe

Date andDocumentVersionChanges Made Summary of ChangesMay 2008v8.0.0No change from previous release. —UG-010852014.24.07Document Revision History8-17U

16550 UART92014.24.07UG-01085SubscribeSend FeedbackCore OverviewThe Altera 16550 UART (Universal Asynchronous Receiver/Transmitter) soft IP core with

Features Run Time Configurable Generate Time ConfigurableEven/Odd parity Yes -Baud rate selection Yes -Priority based interrupt with configu‐rable ena

Table 9-3: Avalon-MM SlavePin Name Width Direction Descriptionaddr 9 InputAvalon-MM Address busHighest addressable byteaddress is 0x118 so a 9-bitwidt

alt_avalon_sgdma_construct_stream_to_mem_desc()...21-20alt_avalon_sgdma_construct_mem_to_stream

Table 9-7: DMA Sideband SignalsPin Name Direction Descriptiondma_tx_ack_n Input TX DMA acknowledgedma_rx_ack_n Input RX DMA acknowledgedma_tx_req_n Ou

Parameter Name Description DefaultFIFO_DEPTHSet depth of FIFOValues limited to 32, 64and 128FIFO_MODE must be 1.128FIFO_HWFC1 = Enabled HardwareFlow C

Resource NumberRouting optimization registers 17Global Signals 2M10k blocks 0Total MLAB memory bits 2432Timing and FmaxFigure 9-2: Maximum Delays on U

16 clock multi-cycle path on the output side. Furthermore, divider of 1 is an unlikely system, if the UARTis clocked at 125 MHz, the resulting baud ra

Reads are expected to have 2 types of behavior:• When status registers are being polled, Reads are expected to be done in singles• When data needs to

data from the shift register is written onto the Receive Buffer. The existing data in the Receive Buffer isoverwritten. This is consistent with publis

Figure 9-5: Hardware Auto Flow-Control Between two UARTsTXFIFOTransmit BufferFlow ControlRXFIFOReceive BufferFlow ControlRXFIFOReceive BufferFlow Cont

Qsys generation, that is to say once FIFO Depth is selected the depth for the FIFO can’t be changeanymore.Table 9-12: Supported FeaturesFeatures Run T

Figure 9-6: Qsys setting to configure FIFO depth16550 UART APIPublic APIsTable 9-13: altera_16550_uart_openPrototype:altera_16550_uart_dev * altera_16

Parameters:dev - The UART deviceptr – destination addresslen – maximum length of the dataflags – for indicating blocking/non-blocking accessfor single