Altera Low Latency Ethernet 10G MAC Instrukcja Użytkownika

Low Latency Ethernet 10G MACUser GuideLast updated for Altera Complete Design Suite: 15.0SubscribeSend FeedbackUG-011442015.05.04101 Innovation DriveS

Getting Started with LL Ethernet 10G MAC22014.12.15UG-01144SubscribeSend FeedbackThis chapter provides a general overview of the Altera IP core design

Signal Direction Width Descriptionmii_rx_d[] Out 4 RX data bus.mii_rx_dv Out 1 When asserted, indicates the RX data is valid.mii_rx_err Out 1 When ass

Signal Direction Width Descriptiontx_egress_timestamp_96b_data[] Out 96 Carries the 96-bit egress timestamp inthe following format:• Bits 48 to 95: 48

Signal Direction Width Descriptiontx_egress_timestamp_64b_fingerprint[]Out n n = value of the Timestampfingerprint width parameter.The fingerprint of

Signal Direction Width Descriptiontx_path_delay_10g_data(for 10 Gbps)In16Connect this bus to the Altera PHYIP. This bus carries the path delay,which i

Signal Direction Width Descriptiontx_etstamp_ins_ctrl_ingress_timestamp_96b[]In 96 96-bit format of ingress timestamp.(48 bits second + 32 bits nanose

Signal Direction Width Descriptiontx_etstamp_ins_ctrl_offset_checksum_field[]In 16 The location of the checksum field,relative to the first byte of th

Signal Direction Width Descriptionrx_ingress_timestamp_64b_data[] Out 64 Carries the 64-bit ingress timestampin the following format:• Bits 16 to 63:

Additional InformationA2014.12.15UG-01144SubscribeSend FeedbackThis section provides additional information about the document and Altera.Low Latency

Date Version ChangesDecember 2014 2014.12.15• Updated the Performance and Resource Utilization table—improvedthe resource utilization for IEEE 1588v2

Date Version ChangesJune 2014 2014.06.30• Improved the performance and resource utilization.• Added a new feature—Unidirectional Ethernet.• Added a ne

Installing and Licensing IP CoresThe Altera IP Library provides many useful IP core functions for your production use without purchasingan additional

7. To generate an HDL instantiation template that you can copy and paste into your text editor, clickGenerate > HDL Example.8. Click Finish. The pa

Related Information• Parameter Settings on page 2-4Parameter SettingsYou customize the MAC IP core by specifying the parameters on the parameter edito

Parameter Value DescriptionNumber of PFC queues 2—8 Specify the number of PFC queues. Thisparameter is only enabled if you turn Enablepriority-based f

Parameter Value DescriptionTimestamp fingerprint width 1–32 Specify the width of the timestamp fingerprintin bits on the transmit path. The default va

Extension Description<variation name>.qip Contains Quartus II project information for your MegaCore functionvariation.<variation name>.bsf

Figure 2-3: Simulation in Quartus II Design FlowPost-fit timing simulation netlist Post-fit timing simulation (3)Post-fit functional simulation net

Altera verifies that the current version of the Quartus II software compiles the previous version of each IPcore. The MegaCore IP Library Release Note

Figure 2-5: Upgrading IP CoresDouble-click to upgrade in editor(no auto upgrade)Upgrade requiredMigration detailsSupports Auto upgradeUpgrade success1

ContentsAbout LL Ethernet 10G MAC... 1-1Features...

6. To regenerate the new IP variation for the new target device, click Generate. When generation iscomplete, click Close.7. Click Finish to complete m

Migration—Maintains 64-bit on Avalon-ST InterfaceThis migration path implements 32-bit to 64-bit adapters on the Avalon ST interface and XGMII, anduse

The timing constraint file uses the set_net_delay to constraint the fitter placement and set_max_skew toperform timing check on the paths. For a proje

Functional Description of LL Ethernet 10G MAC32014.12.15UG-01144SubscribeSend FeedbackThe Low Latency (LL) Ethernet 10G MAC IP core handles the flow o

InterfacesTable 3-1: InterfacesInterfaces DescriptionAvalon-ST InterfaceThe client-side interface of the MAC employs the Avalon-ST protocol,which is a

Figure 3-2: Interface SignalsThe inclusion and width of some signals depend on the operating mode and features selected.MAC RXClock andResetcsr_clkcsr

Frame TypesThe MAC IP core supports the following frame types:• Basic Ethernet frames, including jumbo frames.• VLAN and stacked VLAN frames.• Control

CRC-32 InsertionBy default, the MAC TX computes and inserts CRC-32 checksum into TX frames. The MAC TXcomputes the CRC-32 checksum over frame bytes th

The following figure shows the timing diagram on the Avalon-ST data interfaces where CRC insertion isdisabled on transmit and CRC removal is disabled

An underflow could occur on the Avalon-ST TX interface. An underflow occurs when theavalon_st_tx_valid signal is deasserted in the middle of frame tra

Length Checking...3-14CRC and

Figure 3-6: Endian Conversion55 (1)D5 CC CC EE 01 05 09 0D55(1)55 88 EE AA 00 04 08 0C55(1)55 EE CC 2E 03 07 0B 0FFB 55 EE AA 88 00 02 06 0A 0ECCtx_31

Table 3-2: Register Field and Link StatusBit 0 Register Field Bit 1 Register Field Link Status TX XGMII Interface BehaviorDon't care Don't c

Figure 3-8: Normal Frame with Preamble Passthrough Mode, Padding Bytes Insertion, and SourceAddress Insertion EnabledThe following diagram shows the t

Figure 3-10: Back-to-back Transmission of Normal Frames with Preamble Passthrough Mode EnabledThe following diagram shows back-to-back transmission of

Figure 3-12: Error Condition—Underflow, continuedtx_312_5_clkavalon_st_tx_startofpacketavalon_st_tx_validavalon_st_tx_readyavalon_st_tx_endofpacketava

RX DatapathThe MAC RX receives Ethernet frames from the XGMII and forwards the payload with relevant framefields to the client after performing checks

Address CheckingThe MAC RX can accept frames with the following address types:• Unicast address—bit 0 of the destination address is 0.• Multicast addr

Frame LengthThe frame length must be at least 64 (0x40) bytes and not exceed the following maximum value for thedifferent frame types:• Basic—The valu

Overflow HandlingWhen an overflow occurs on the client side, the client can backpressure the Avalon-ST receive interfaceby deasserting the avalon_st_r

Figure 3-16: Back-to-back Transmission of Normal Frames with Preamble Passthrough Mode EnabledThe following diagram shows back-to-back reception of no

PHY-side Interfaces...

To use the IEEE 802.3 flow control, set the following registers:• On the transmit datapath:• Set tx_pfc_priority_enable to 0 to disable the PFC.• Set

The following figure shows the transmission of an XON pause frame. The MAC sets the destinationaddress field to the global multicast address, 01-80-C2

PFC Frame ReceptionWhen the MAC RX receives a PFC frame from the remote partner, it asserts theavalon_st_rx_pfc_pause_data[n] signal if Pause Quanta n

Figure 3-18: CSR Resetcsr, tx, rx clockscsr_rst_ntx_rst_nrx_rst_nWhen you assert csr_rst_n , you must also assert tx_rst_n and rx_rst_n . Hold the re

Table 3-4: Supported PHYsOperating Mode PHY10G 10GBASE-R PHY, XAUI PHY1G/10G10GBASE-KR or 1G/10G PHY10M/100M/1G/10GTo connect the MAC IP core to 64-bi

Figure 3-19: PHY Configuration with 10GBASE-R Register Mode Enabled.Figure shows a block diagram of the PHY configuration when operating in 10GBASE-R

Figure 3-20: Fault SignalingRemote Fault (0x9c000002)Idle (07070707)Remote Fault (0x9c000002)ClientInterfaceMACTxRS TxMACRxRS Rx2link_fault_status_xgm

IEEE 1588v2The IEEE 1588v2 option provides time stamp for receive and transmit frames in the LL Ethernet 10GMAC IP core designs. The feature consists

Figure 3-22: Overview of IEEE 1588v2 FeatureIEEE 1588v2Tx LogicIEEE 1588v2Rx LogicPTP SoftwareStackTime-of-DayClockPHYTxPHYRx10GbE MAC IP10GBASE-R PHY

Table 3-5: Timestamp and Correction Insertion for 1-Step Clock SynchronizationPTP MessageOrdinary Clock Boundary ClockE2E TransparentClockP2P Transpar

About LL Ethernet 10G MAC12014.12.15UG-01144SubscribeSend FeedbackThe Altera® Low Latency (LL) Ethernet 10G (10GbE) Media Access Controller (MAC) IP c

Figure 3-23: PTP Packet in IEEE 802.3flagFieldcorrectionFieldtransportSpecific | messageTypereserved | versionPTPreserved1 Octet1 Octet1 Octet2 Octets

Figure 3-24: PTP Packet over UDP/IPv4MAC HeaderUDP HeaderIP HeaderPTP HeaderTime To LiveProtocol = 0x11Version | Internet Header LengthDifferentiated

Figure 3-25: PTP Packet over UDP/IPv6Version | Traffic Class | Flow LabelPayload Length4 Octet2 OctetsSource IP Address16 OctetsDestination IP Address

Configuration Registers for LL Ethernet 10GMAC42014.12.15UG-01144SubscribeSend FeedbackThe LL Ethernet 10G MAC IP core provides a total of 4Kb registe

Mapping 10-Gbps Ethernet MAC Registers to LL Ethernet 10G MAC RegistersUse this table to map the legacy Ethernet 10-Gbps MAC registers to the LL Ether

Register Names (10-Gbps Ethernet MAC)Offset(10-Gbps Ethernet MAC)Offset(LL Ethernet 10G MAC)TX Address Insertion Control 1200 02ATX Address Insertion

Register Names (10-Gbps Ethernet MAC)Offset(10-Gbps Ethernet MAC)Offset(LL Ethernet 10G MAC)TX Period for 10G 1110 100TX Fractional Nano-second Adjust

Access DefinitionRW1C Read and write 1 to clear. Writing 0 has no effect. Writing 1 clears the bit if the bit hasbeen set to 1 by the IP core. The cli

Table 4-5: MAC Reset Control RegisterWordOffsetRegister Name Description Access HW ResetValue0x001F mac_reset_control The user application can use the

WordOffsetRegister Name Description Access HW ResetValue0x0022 tx_transfer_statusThe MAC sets the following bits to indicatethe status of the TX datap

FeaturesThe LL Ethernet 10G MAC supports the following features:• Full-duplex MAC in four operating modes: 10G, 1G/10G, or 10M/100M/1G/10G).• Three v

WordOffsetRegister Name Description Access HW ResetValue0x0028 tx_preamble_control(4)• Bit 0—configures the preamblepassthrough mode on transmit.0: Di

WordOffsetRegister Name Description Access HW ResetValue0x002D tx_vlan_detection• Bit 0—TX VLAN detection disable.0: The MAC detects VLAN and stackedV

Flow Control RegistersTable 4-7: Flow Control RegistersWordOffsetRegister Name Description Access HW ResetValue0x0040 tx_pauseframe_control• Bits 1:0—

WordOffsetRegister Name Description Access HW ResetValue0x0044 tx_pauseframe_enable• Bit 0—configures the transmission ofpause frames. This bit affect

WordOffsetRegister Name Description Access HW ResetValue0x0058 pfc_holdoff_quanta_0(5)Specifies the gap between two consecutivetransmissions of XOFF p

RX Configuration and Status RegistersTable 4-9: RX Configuration and Status RegistersWordOffsetRegister Name Description Access HW ResetValue0x00A0 rx

WordOffsetRegister Name Description Access HW ResetValue0x00A6 rx_crccheck_control CRC checking on receive.• Bit 0—always set this bit to 0.• Bit 1—CR

WordOffsetRegister Name Description Access HW ResetValue0x00AC rx_frame_controlConfigure this register before you enablethe MAC IP core for operations

WordOffsetRegister Name Description Access HW ResetValue0x00AC rx_frame_controlBit 16—EN_SUPP00: Disables the use of supplementaryaddress 0.1: Enables

WordOffsetRegister Name Description Access HW ResetValue0x00B0 rx_frame_spaddr0_0 You can specify up to four 6-bytesupplementary addresses:• rx_framed

Release InformationThe following table lists information about this release of the LL Ethernet 10G MAC IP core.Table 1-1: Release InformationItem Desc

WordOffsetRegister Name Description Access HW ResetValue0x00FCrx_pktovrflow_error36-bit error counter that collects thenumber of RX frames that are tr

Table 4-10: TX Timestamp RegistersWordOffsetRegister Name Description Access HW ResetValue0x0100 tx_period_10GSpecifies the clock period for thetimest

WordOffsetRegister Name Description Access HW ResetValue0x10A tx_fns_adjustment_mult_speedStatic timing adjustment in fractionalnanoseconds on the TX

Step Description 10G 10M, 100M or 1G2 Convert the digitallatency in UI to ns.123 UI * 0.097 = 11.931 ns 53 UI * 0.8 = 42.4 ns3 Add the analog latencyt

Table 4-14: RX Timestamp RegistersWordOffsetRegister Name Description Access HW ResetValue0x0120 rx_period_10GSpecifies the clock period on the RXdata

WordOffsetRegister Name Description Access HW ResetValue0x12A rx_fns_adjustment_mult_speedStatic timing adjustment in fractionalnanoseconds on the RX

Table 4-16: Example: Calculating Timing Adjustments for 10M – 10GbE Design in Stratix V DeviceStep Description 10G 10M, 100M or 1G1 Identify the digit

Table 4-18: ECC RegistersWord Offset Register Name Description Access HW ResetValue0x0240 ecc_status• Bit 0—a value of '1' indicates that an

Memory-based statistics counters may not be accurate when the MAC IP core receives or transmits back-to-back undersized frames. On the TX datapath, yo

WordOffsetRegister Name Description Access HW ResetValue0x014Atx_stats_pauseMACCtrl_Frames36-bit statistics counter that collectsthe number of valid p

Configuration Arria V GX/GT/GZArria 10 Stratix V10G MAC with Arria 10 Transceiver Native PHYpresets:• 10GBASE-R• 10GBASE-R Low Latency• 10GBASE-R Regi

WordOffsetRegister Name Description Access HW ResetValue0x0158tx_stats_broadcast_FramesErr36-bit statistics counter that collectsthe number of broadca

WordOffsetRegister Name Description Access HW ResetValue0x0166tx_stats_etherStatsPkts128to255Octets36-bit statistics counter that collectsthe number o

WordOffsetRegister Name Description Access HW ResetValue0x0172tx_stats_etherStatsJabbers36-bit statistics counter that collectsthe number of oversized

Interface Signals for LL Ethernet 10G MAC52014.12.15UG-01144SubscribeSend FeedbackRelated InformationInterfaces on page 3-2Overview of the interfaces

Signal OperatingModeDirection Width Descriptiontx_156_25_clk 10G, 1G/10G,10M/100M/1G/10GIn 1156.25-MHz clock for the MAC TXdatapath when you choose to

Signal OperatingModeDirection Width Descriptionrx_rst_n All In 1Active-low reset for the MAC RXdatapath.csr_clk 10G, 1G/10G,10M/100M/1G/10GIn 1 Clock

Table 5-3: Error Correction SignalsSignal Direction Width Descriptionecc_err_det_corr Out 1 The MAC IP core can indicate detected andcorrected ECC err

Signal Direction Width Descriptioncsr_read In 1 Assert this signal to request a read.csr_readdata[] Out 32 Data read from the specified register. The

Signal Direction Width Descriptionavalon_st_tx_empty[]In 2 Use this signal to specify the number of empty bytes(not used) in the cycle that contain th

Signal Direction Width Descriptionavalon_st_rx_empty[]Out 2/3Contains the number of empty bytes during thecycle that contain the end of the RX data.Th

MAC SettingsALMs ALUTsLogicRegistersMemory BlockOperatingModeEnabled Options10M/100M/1G/10GTimestampingand memory-based statisticscounters.Time of day

Signal Direction Width Descriptionavalon_st_tx_pfc_gen_data[]In n(4–16)n = 2 x Number of PFC queues parameter.Each pair of bits is associated with a p

Table 5-9: Avalon-ST TX Status SignalsSignal Direction Width Descriptionavalon_st_txstatus_validOut 1 When asserted, this signal qualifies the avalon_

Signal Direction Width Descriptionavalon_st_tx_pfc_status_data[]Out n(4 - 16)n = 2 x Number of PFC queues parameterWhen set to 1, the respective bit i

Signal Direction Width Descriptionavalon_st_rxstatus_data[]Out 40Contains information about the RX frame.• Bits 0 to 15: Payload length.• Bits 16 to 3

Signal Direction Width Descriptionavalon_st_rx_pfc_status_data[]Out n(4 - 16)n = 2 x Number of PFC queues parameterWhen set to 1, the respective bit i

Signal Condition Direction Width Descriptionxgmii_tx_control[]Use legacy Ethernet10G MAC XGMIIinterface disabled.Enable 10GBASE-Rregister modedisabled

Signal Condition Direction Width Descriptionxgmii_tx[] Use legacy Ethernet10G MAC XGMIIinterface enabled.Out 728-lane SDR XGMII transmit data andcontr

XGMII RX SignalsTable 5-12: XGMII Receive SignalsSignal Condition Direction Width Descriptionxgmii_rx_data[]Use legacy Ethernet10G MAC XGMIIinterface

Signal Condition Direction Width Descriptionxgmii_rx_validUse legacy Ethernet10G MAC XGMIIinterface disabled.Enable 10GBASE-Rregister modeenabled.In 1

GMII RX SignalsTable 5-14: GMII RX SignalsSignal Direction Width Descriptiongmii_rx_clk In 1 125-MHz RX clock.gmii_rx_d[] In 8 RX data.gmii_rx_dv In 1