Altera IP Compiler for PCI Express Instrukcja Użytkownika Pobierz pdf (Strona 109)

Chapter 5: IP Core Interfaces 5–23

Avalon-ST Interface

August 2014 Altera Corporation IP Compiler for PCI Express User Guide

Clock Signals—Hard IP Implementation

Table 5–5 describes the clock signals that comprise the clock interface used in the hard

IP implementation.

Refer to Chapter 7, Reset and Clocks for a complete description of the clock interface

for each IP Compiler for PCI Express variation.

Clock Signals—Soft IP Implementation

Table 5–5. Clock Signals Hard IP Implementation (Note 1)

Signal I/O Description

refclk

Reference clock for the IP core. It must be the frequency specified on the System Settings page

accessible from the Parameter Settings tab using the parameter editor.

pld_clk

Clocks the application layer and part of the adapter. You must drive this clock from

core_clk_out

This is a fixed frequency clock used by the data link and transaction layers. To meet PCI Express

link bandwidth constraints, it has minimum frequency requirements which are outlined in

Table 7–1 on page 7–7.

pclk_in

This is used for simulation only, and is derived from the

refclk

. It is the PIPE interface clock

used for PIPE mode simulation.

clk250_out

O This is used for simulation only. The testbench uses this to generate

pclk_in

clk500_out

O This is used for simulation only. The testbench uses this to generate

pclk_in

Note to Table 5–5:

(1) These clock signals are illustrated by Figure 7–5 on page 7–6.

Table 5–6. Clock Signals Soft IP Implementation (Note 1)

Signal I/O Description

refclk

Reference clock for the IP core. It must be the frequency specified on the System Settings

page accessible from the Parameter Settings tab using the parameter editor.

clk125_in

Input clock for the ×1 and ×4 IP core. All of the IP core I/O signals (except

refclk

clk125_out

, and

npor

) are synchronous to this clock signal. This signal must be connected

to the

clk125_out

signal. This signal is not on the ×8 IP core.

clk125_out

Output clock for the ×1 and ×4 IP core. 125-MHz clock output derived from the

refclk

input.

This signal is not on the ×8 IP core.

clk250_in

Input clock for the ×8 IP core. All of the IP core I/O signals (except

refclk

clk250_out

, and

npor

) are synchronous to this clock signal. This signal must be connected to the

clk250_out

signal.

clk250_out

Output from the ×8 IP core. 250 MHz clock output derived from the

refclk

input. This signal

is only on the ×8 IP core.

Note to Table 5–6:

(1) Refer to Figure 7–6 on page 7–9.

1 2 ... 104 105 106 107 108 109 110 111 112 113 114 ... 371 372

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