Altera IP Compiler for PCI Express Instrukcja Użytkownika Pobierz pdf (Strona 120)

5–34 Chapter 5: IP Core Interfaces

Avalon-ST Interface

IP Compiler for PCI Express User Guide August 2014 Altera Corporation

Table 5–15 describes the configuration space registers referred to in Table 5–13 and

Table 5–14.

Table 5–15. Configuration Space Register Descriptions (Part 1 of 3)

Reference

cfg_devcsr

cfg_dev2csr

32 O

cfg_devcsr[31:16]

is status and

cfg_devcsr[15:0]

is device

control for the PCI Express capability structure.

cft_dev2csr[31:16]

is status 2 and

cfg_dev2csr[15:0]

device control 2 for the PCI Express capability structure.

Table 6–7 on

page 6–4

0x088 (Gen1)

Table 6–8 on

page 6–5

0x0A8 (Gen2)

cfg_slotcsr

16 O

cfg_slotcsr[31:16]

is the slot control and

cfg_slotcsr[15:0]

is the slot status of the PCI Express

capability structure. This register is only available in root port

mode.

Table 6–7 on

page 6–4

0x098 (Gen1)

Table 6–8 on

page 6–5

0x098 (Gen2)

cfg_linkcsr

32 O

cfg_linkcsr[31:16]

is the primary link status and

cfg_linkcsr[15:0]

is the primary link control of the PCI

Express capability structure.

Table 6–7 on

page 6–4

0x090 (Gen1)

Table 6–8 on

page 6–5

0x090 (Gen2)

cfg_link2csr

cfg_link2csr[31:16]

is the secondary link status and

cfg_link2csr[15:0]

is the secondary link control of the PCI

Express capability structure which was added for Gen2.

When

tl_cfg_addr=2

tl_cfg_ctl

returns the primary and

secondary link control registers,

{cfg_linkcsr[15:0],

cfg_lin2csr[15:0]}

, the primary link status register,

cfg_linkcsr[31:16]

, is available on

tl_cfg_sts[46:31]

For Gen1 variants, the link bandwidth notification bit is always set

to 0. For Gen2 variants, this bit is set to 1.

Table 6–8 on

page 6–5

0x0B0 (Gen2,

only)

cfg_prmcsr

16 O

Base/Primary control and status register for the PCI configuration

space.

Table 6–2 on

page 6–2

0x004 (Type 0)

Table 6–3 on

page 6–3

0x004 (Type 1)

cfg_rootcsr

Root control and status register of the PCI-Express capability. This

Table 6–7 on

page 6–4

0x0A0 (Gen1)

Table 6–8 on

page 6–5

0x0A0 (Gen2)

cfg_seccsr

16 O

Secondary bus control and status register of the PCI-Express

capability. This register is only available in root port mode.

Table 6–3 on

page 6–3

0x01C

1 2 ... 115 116 117 118 119 120 121 122 123 124 125 ... 371 372

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