Altera IP Compiler for PCI Express Instrukcja Użytkownika Pobierz pdf (Strona 248)

15–16 Chapter 15: Testbench and Design Example

Chaining DMA Design Example

IP Compiler for PCI Express User Guide August 2014 Altera Corporation

Table 15–9 describes the fields in the DMA read status high register. All of these fields

are read only.

[23:21] Max payload size

The following encodings are defined:

■ 001 128 bytes

■ 001 256 bytes

■ 010 512 bytes

■ 011 1024 bytes

■ 100 2048 bytes

[20:17] Reserved —

16 Write DMA descriptor FIFO empty Indicates that there are no more descriptors pending in the write DMA.

[15:0] Write DMA EPLAST Indicates the number of the last descriptor completed by the write DMA.

Table 15–8. Fields in the DMA Write Status High Register

Bit Field Description

Table 15–9. Fields in the DMA Read Status High Register

Bit Field Description

[31:25] Board number

Indicates to the software application which board is being used. The

following encodings are defined:

■ 0 Altera Stratix II GX ×1

■ 1 Altera Stratix II GX ×4

■ 2 Altera Stratix II GX ×8

■ 3 Cyclone II ×1

■ 4 Arria GX ×1

■ 5 Arria GX ×4

■ 6 Custom PHY ×1

■ 7 Custom PHY ×4

24 Reserved —

[23:21] Max Read Request Size

The following encodings are defined:

■ 001 128 bytes

■ 001 256 bytes

■ 010 512 bytes

■ 011 1024 bytes

■ 100 2048 bytes

[20:17] Negotiated Link Width

The following encodings are defined:

■ 0001 ×1

■ 0010 ×2

■ 0100 ×4

■ 1000 ×8

16 Read DMA Descriptor FIFO Empty Indicates that there are no more descriptors pending in the read DMA.

[15:0] Read DMA EPLAST Indicates the number of the last descriptor completed by the read DMA.

1 2 ... 243 244 245 246 247 248 249 250 251 252 253 ... 371 372

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