Altera IP Compiler for PCI Express Instrukcja Użytkownika Pobierz pdf (Strona 143)

Chapter 5: IP Core Interfaces 5–57

Physical Layer Interface Signals

August 2014 Altera Corporation IP Compiler for PCI Express User Guide

for simulation of the PIPE interface for variations using an internal transceiver. In

Table 5–31, signals that include lane number 0 also exist for lanes 1-7, as marked in the

table. Refer to Chapter 14, External PHYs for descriptions of the slightly modified

PIPE interface signalling for use with specific external PHYs. The modifications

include DDR signalling and source synchronous clocking in the TX direction.

Table 5–31. PIPE Interface Signals (Part 1 of 2)

Signal Name in

Qsys

I/O Description

txdata<n>_ext[15:0]/

pipe_ext_txdata0_ext[15:0] (1)

Transmit data

n> (2 symbols on lane

n>). This bus transmits data on

lane

n>. The first transmitted symbol is

txdata_ext[7:0]

and the

second transmitted symbol is

txdata0_ext[15:8]

. For the 8-bit PIPE

mode only txdata

n>_ext[7:0] is available.

txdatak<n>_ext[1:0]/

pipe_ext_txdatak<n>_ext[1:0] (1)

Transmit data control

n> (2 symbols on lane

n>). This signal serves

as the control bit for

txdata<

_ext

;

txdatak<

_ext[0]

for the

first transmitted symbol and

txdatak<

_ext[1]

for the second

(8B/10B encoding). For 8-bit PIPE mode only the single bit signal

txdatak<

n>_

ext

is available.

txdetectrx<n>_ext/

pipe_ext_txdetectrx<n>_ext

(1)

Transmit detect receive

n>. This signal tells the PHY layer to start a

receive detection operation or to begin loopback.

txelecidle<n>_ext/

pipe_ext_txelecidle<n>_ext

(1)

Transmit electrical idle

n>. This signal forces the transmit output to

electrical idle.

txcompl<n>_ext/

pipe_ext_txcompl<n>_ext

(1)

Transmit compliance

n>. This signal forces the running disparity to

negative in compliance mode (negative COM character).

rxpolarity<n>_ext/

pipe_ext_rxpolarity<n>_ex

(1)

Receive polarity

n>. This signal instructs the PHY layer to do a polarity

inversion on the 8B/10B receiver decoding block.

powerdown<n>_ext[1:0]/

pipe_ext_powerdown<n>_ext[1:0]

(1)

Power down

n>. This signal requests the PHY to change its power state

to the specified state (P0, P0s, P1, or P2).

tx_pipemargin/

internal signal in Qsys O

Transmit V

margin selection. The IP Compiler for PCI Express hard IP

sets the value for this signal based on the value from the Link Control 2

tx_pipedeemph/internal signal in

Qsys

Transmit de-emphasis selection. In PCI Express Gen2 (5 Gbps) mode it

selects the transmitter de-emphasis:

■ 1'b0: -6 dB

■ 1'b1: -3.5 dB

The PCI Express IP core hard IP sets the value for this signal based on

the indication received from the other end of the link during the Training

Sequences (TS). You do not need to change this value.

rxdata<n>_ext[15:0]/

pipe_ext_rxdata<n>_ext[15:0]

(1) (2)

Receive data

n> (2 symbols on lane

n>). This bus receives data on

lane

n>. The first received symbol is

rxdata<

_ext[7:0]

and the

second is

rxdata<

_ext[15:8]

. For the 8 Bit PIPE mode only

rxdata<

_ext[7:0]

is available.

rxdatak<n>_ext[1:0]/

pipe_ext_rxdatak<n>_ext[1:0]

(1) (2)

Receive data control

n> (2 symbols on lane

n>). This signal separates

control and data symbols. The first symbol received is aligned with

rxdatak<

_ext[0]

and the second symbol received is aligned with

rxdata<

_ext[1]

. For the 8 Bit PIPE mode only the single bit signal

rxdatak<

_ext

is available.

rxvalid<n>_ext

(1) (2) I

Receive valid

n>. This symbol indicates symbol lock and valid data on

rxdata<

_ext

and

rxdatak<

_ext

1 2 ... 138 139 140 141 142 143 144 145 146 147 148 ... 371 372

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