Altera LVDS SERDES Transmitter / Receiver Instrukcja Użytkownika Pobierz pdf (Strona 12)

Option Description

Use External PLL

Turn on this option to use an external PLL to clock the

SERDES transmitter. When you turn on this option, the

options on the Frequency/PLL settings page are disabled. You

must use a separate PLL to provide the clocking source and

make the necessary connections. You must ensure your circuit

has the correct input and functionality to generate an

appropriate clock frequency and is correctly connected to the

LVDS transmitter.

When you have a deserialization factor of two, the IP core

bypasses SERDES and implements the SERDES functionality in

DDR registers. Your design requires a deserialization factor of

at least four to turn on the external PLL option.

If you turn off this option, the IP core automatically

implements an internal PLL to clock the ALTLVDS_TX block.

For Stratix and Stratix GX devices, if you implement SERDES

for your LVDS transmitter using a dedicated SERDES block,

you do not have the option to use an external PLL.

Use 'tx_data_reset' input port

This option is available when you implement the LVDS in logic

cells. When you turn on this option, it adds an input port in the

IP core, which when asserted asynchronously resets all the logic

in the ALTLVDS_TX IP core excluding the PLL.

Frequency/ PLL Settings (page 4)

The options on this page are available only when you are using internal PLL

What is the output data rate? Specifies the data rate for the output channel of the transmitter,

in Megabits per second (Mbps). For data rate ranges, refer to

the Device Data Sheet chapter in the relevant device handbook.

This option determines the legal value of the input clock rate.

Specify input clock rate by Specifies the clock frequency (tx_inclock port) or the clock

(inclock_period parameter) going into the internal PLL. The

legal values depend on the output data rate selected.

What is the phase alignment of 'tx_in'

with respect to the rising edge of 'tx_

inclock'? (in degrees)

Determines the phase alignment of the data transmitted by the

core logic array with respect to the tx_inclock clock.

The available values are 0.00, 22.50, 45.00, 67.50, 90.00,

112.50, 135.00, 157.50, 180.00, 202.50, 225.00, 247.50, 270.00,

292.50, 315.00, and 337.50.

The values for this option are device dependent.

ALTLVDS_TX Parameter Settings

UG-MF9504

2014.12.15

Altera Corporation

LVDS SERDES Transmitter/Receiver IP Cores User Guide

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