Altera Mentor Verification IP Altera Edition AMBA AXI4-Li Instrukcja Użytkownika Pobierz pdf (Strona 118)

Mentor Verification IP AE AXI4-Lite User Guide, V10.3

118

SystemVerilog Tutorials

Verifying a Slave DUT

April 2014

Example 6-1 shows the configuration of the master_ready_delay_mode to its default value.

Example 6-1. master_ready_delay_mode

// Enum type for master ready delay mode

// AXI4_VALID2READY - Ready delay for a phase will be applied from

// start of phase (Means from when VALID is asserted).

// AXI4_TRANS2READY - Ready delay will be applied from the end of

// previous phase. This might result in ready before valid.

typedef enum bit

{

AXI4_VALID2READY = 1'b0,

AXI4_TRANS2READY = 1'b1

} axi4_master_ready_delay_mode_e;

// Master ready delay mode selection : default it is VALID2READY

axi4_master_ready_delay_mode_e master_ready_delay_mode =

AXI4_VALID2READY;

m_wr_resp_phase_ready_delay

The m_wr_resp_phase_ready_delay variable holds the BREADY signal delay. The delay value

extends the length of the write response phase by a number of ACLK cycles. The starting point

of the delay is determined by the master_ready_delay_mode variable configuration.

Example 6-2 shows the AWREADY signal delayed by two ACLK cycles. You can edit this

variable to change the AWREADY signal delay.

Example 6-2. m_wr_resp_phase_ready_delay

// Variable : m_wr_resp_phase_ready_delay

int m_wr_resp_phase_ready_delay = 2;

m_rd_data_phase_ready_delay

The m_rd_data_phase_ready_delay variable holds the RREADY signal delay. The delay value

extends the length of each read data phase (beat) by a number of ACLK cycles. The starting

point of the delay is determined by the master_ready_delay_mode variable configuration.

Example 6-3 shows the RREADY signal delayed by two ACLK cycles. You can edit this

variable to change the RREADY signal delay.

Example 6-3. m_rd_data_phase_ready_delay

// Variable : m_rd_data_phase_ready_delay

int m_rd_data_phase_ready_delay = 2;

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