Altera Mentor Verification IP Altera Edition AMBA AXI4-Li Instrukcja Użytkownika Strona 34
- Strona / 413
- Spis treści
- BOOKMARKI
Oceniono. / 5. Na podstawie oceny klientów
Mentor Verification IP AE AXI4-Lite User Guide, V10.3
34
SystemVerilog API Overview
Access Transaction Record
April 2014
get*_transaction(), get*_phase(), get*_cycle()
A slave BFM test program can use a received write address phase to form the response to the
write transaction. The test program gets the write address phase for the transaction by calling
the get_write_addr_phase() task. This task blocks until it has received the address phase,
allowing the test program to call the execute_write_response_phase() task for the transaction at
a later stage, as shown in the slave BFM test program in Example 2-2.
Example 2-2. Slave Test Program Using get_write_addr_phase()
slave_trans = bfm.create_slave_transaction();
bfm.get_write_addr_phase(slave_trans);
...
bfm.execute_write_response_phase(slave_trans);
Note
Not all BFM APIs support the full complement of get*_transaction(), get*_phase(),
get*_cycle() tasks. Refer to the individual master, slave, or monitor BFM API for details.
Access Transaction Record
Each BFM API has tasks that can access a complete or partially complete Transaction Record.
The set*() and get*() tasks are used in a test program to set and get information from the
transaction record.
Note
The set*() and get*() tasks are not explicitly described in each BFM API chapter. The
simple rule for the task name is set_ or get_ followed by the name of the transaction field
accessed. Refer to “Transaction Fields” on page 30 for transaction field name details.
set*()
For example, to set the WSTRB write strobes signal in the Transaction Record of a write
transaction, the master test program would use the set_write_strobes() task, as shown in the
following code:
write_trans.set_write_strobes(4'b0010);
get*()
For example, a slave BFM test program uses a received write address phase to get the
AWPROT signal value from the Transaction Record, as shown in the following slave BFM test
program code:
- AMBA AXI4-Lite 1
- User Guide 1
- Table of Contents 10
- List of Examples 12
- List of Figures 14
- List of Tables 15
- About This User Guide 17
- Protocol Restrictions 17
- Supported Simulators 18
- Simulator GCC Requirements 18
- Chapter 1 21
- Mentor VIP Altera Edition 21
- What Is a Transaction? 22
- AXI4-Lite Transactions 22
- Chapter 2 27
- SystemVerilog API Overview 27
- Chapter 3 39
- SystemVerilog Master BFM 39
- SystemVerilog Master API 43
- Returns 44
- Example 58
- Chapter 4 63
- SystemVerilog Slave BFM 63
- SystemVerilog Slave API 68
- Arguments config_name 69
- Chapter 5 91
- SystemVerilog Monitor API 96
- Prototype 100
- Arguments 100
- April 2014 102
- SystemVerilog Monitor BFM 105
- Helper Functions 111
- SystemVerilog Tutorials 115
- Chapter 6 115
- BFM Master Test Program 116
- Verifying a Slave DUT 117
- Verifying a Master DUT 123
- Basic Slave API Definition 124
- *_valid_delay = 4 127
- *_ready_delay = 2 127
- Advanced Slave API Definition 129
- Initial Block 131
- Chapter 7 137
- VHDL API Overview 137
- Test Program VHDL 138
- Configuration 139
- Creating Transactions 139
- Transaction Definition 140
- Executing Transactions 144
- Waiting Events 145
- Access Transaction Record 146
- Operation Mode 147
- Channel Handshake Delay 147
- Handshake Delay 148
- Transaction Done 149
- Chapter 8 151
- VHDL Master BFM 151
- Master BFM Protocol Support 152
- Master Timing and Events 152
- Master BFM Configuration 152
- Master Assertions 155
- VHDL Master API 156
- Chapter 9 213
- VHDL Slave BFM 213
- Slave BFM Configuration 214
- Slave Assertions 216
- VHDL Slave API 217
- Operational 223
- Transaction 223
- Chapter 10 279
- VHDL Monitor BFM 279
- Monitor BFM Configuration 280
- Monitor Assertions 282
- VHDL Monitor API 283
- Chapter 11 335
- VHDL Tutorials 335
- BFM Slave Test Program 341
- Chapter 12 353
- Running the Qsys Tool 356
- Running a Simulation 359
- ModelSim Simulation 360
- Editing the modelsim.ini File 363
- Questa Simulation 364
- Cadence IES Simulation 364
- Synopsys VCS Simulation 366
- Appendix A 369
- AXI4-Lite Assertions 384
- Appendix B 385
- SystemVerilog Test Programs 385
- Appendix C 397
- VHDL Test Programs 397
- End-User License Agreement 409
Powiązane produkty i podręczniki dla Urządzenia pomiarowe Altera Mentor Verification IP Altera Edition AMBA AXI4-Li
Urządzenia pomiarowe Altera Mentor Verification IP Altera Edition AMBA AXI4-St Instrukcja Użytkownika
(231 strony)
(231 strony)
Urządzenia pomiarowe Altera Mentor Verification IP Altera Edition AMBA AXI3/4T Instrukcja Użytkownika
(783 strony)
(783 strony)
Urządzenia pomiarowe Altera PCI Development Kit, Cyclone II Edition Getting St Instrukcja Użytkownika
(40 strony)
(40 strony)
Urządzenia pomiarowe Altera PCI Express Development Kit, Stratix II GX Edition Instrukcja Użytkownika
(36 strony)
(36 strony)
© 2020, manymanuals.pl. Wszelkie prawa zastrzeżone. | 0.030 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Komentarze do niniejszej Instrukcji