Altera PowerPlay Early Power Estimator Instrukcja Użytkownika Pobierz pdf (Strona 18)

3–6 Chapter 3: Using Cyclone III PowerPlay Early Power Estimator

PowerPlay Early Power Estimator Inputs

PowerPlay Early Power Estimator User Guide for Cyclone III FPGAs © June 2009 Altera Corporation

Figure 3–4 shows the Logic section in the PowerPlay Early Power Estimator and the

estimated power consumed by the logic.

RAM Blocks

Cyclone III device family feature M9K RAM blocks.

Each row in the RAM section represents a design module where the RAM blocks have

the same data width, RAM depth, RAM mode, port parameters, and output toggle

rate. If some or all the RAM blocks in your design have different configurations, enter

the information in different rows. For each design module, you must enter the

number of RAM blocks, the data width, the RAM mode, and the output toggle rate.

You must also enter the following parameters for each port:

■ Clock frequency (in MHz)

■ The percentage of time the RAM clock is enabled

■ The percentage of time the port is writing compared to reading

Figure 3–3. 4-Bit Counter Example

PRN

CLRN

TFF

PRN

CLRN

TFF

PRN

CLRN

TFF

PRN

CLRN

TFF

cout2

cout1

cout0

clock

cout3

OUTPUT

cout0cout0

OUTPUT

cout3cout3

OUTPUT

cout2cout2

OUTPUT

cout1cout1

Figure 3–4. Logic Section in the PowerPlay Early Power Estimator

1 2 ... 13 14 15 16 17 18 19 20 21 22 23 ... 41 42

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