Altera PowerPlay Early Power Estimator Instrukcja Użytkownika Pobierz pdf (Strona 24)

3–12 Chapter 3: Using Cyclone III PowerPlay Early Power Estimator

PowerPlay Early Power Estimator Inputs

PowerPlay Early Power Estimator User Guide for Cyclone III FPGAs © June 2009 Altera Corporation

Figure 3–7 shows a graphical representation of the I/O power consumption. The I

CCIO

rail power includes both the thermal P

and external P

REF

pins consume minimal current (less than 10 A) that is negligible when

compared to the power consumed by the general purpose I/O pins. Therefore, the

PowerPlay Early Power Estimator does not include the current for V

REF

pins in the

calculations.

Each row in the I/O section represents a design module where the I/O pins have the

same I/O standard, current strength or output termination, data rate, clock frequency,

output enable static probability, and capacitive load. You must enter the following

parameters for each design module:

■ I/O standard

■ Current Strength/Output Termination

■ Number of input, output, and bidirectional pins

■ I/O data rate

■ Clock frequency (f

MAX

) in MHz

■ Average pin toggle percentage

■ Output enable static probability

■ Capacitance of the load

Figure 3–7. I/O Power Representation

Cyclone III Device

CCINT

CCIO

CCINT

CCIO

Thermal P

INT

Thermal P

External P

1 2 ... 19 20 21 22 23 24 25 26 27 28 29 ... 41 42

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Altera PowerPlay Early Power Estimator Instrukcja Użytkownika Strona 24