Altera Stratix V Advanced Systems Development Board Instrukcja Użytkownika Pobierz pdf (Strona 49)

Chapter 2: Board Components 2–39

Components and Interfaces

January 2014 Altera Corporation Stratix V Advanced Systems Development Board

Reference Manual

HSMC_RX_N0

1.4-V PCML AB44 Transceiver receive channel

HSMC_RX_P1

1.4-V PCML Y43 Transceiver receive channel

HSMC_RX_N1

1.4-V PCML Y44 Transceiver receive channel

HSMC_RX_P2

1.4-V PCML V43 Transceiver receive channel

HSMC_RX_N2

1.4-V PCML V44 Transceiver receive channel

HSMC_RX_P3

1.4-V PCML T43 Transceiver receive channel

HSMC_RX_N3

1.4-V PCML T44 Transceiver receive channel

HSMC_RX_P4

1.4-V PCML M43 Transceiver receive channel

HSMC_RX_N4

1.4-V PCML M44 Transceiver receive channel

HSMC_RX_P5

1.4-V PCML K43 Transceiver receive channel

HSMC_RX_N5

1.4-V PCML K44 Transceiver receive channel

HSMC_RX_P6

1.4-V PCML H43 Transceiver receive channel

HSMC_RX_N6

1.4-V PCML H44 Transceiver receive channel

HSMC_RX_P7

1.4-V PCML F43 Transceiver receive channel

HSMC_RX_N7

1.4-V PCML F44 Transceiver receive channel

HSMC_TX_P0

1.4-V PCML W41 Transceiver transmit channel

HSMC_TX_N0

1.4-V PCML W42 Transceiver transmit channel

HSMC_TX_P1

1.4-V PCML U41 Transceiver transmit channel

HSMC_TX_N1

1.4-V PCML U42 Transceiver transmit channel

HSMC_TX_P2

1.4-V PCML R41 Transceiver transmit channel

HSMC_TX_N2

1.4-V PCML R42 Transceiver transmit channel

HSMC_TX_P3

1.4-V PCML N41 Transceiver transmit channel

HSMC_TX_N3

1.4-V PCML N42 Transceiver transmit channel

HSMC_TX_P4

1.4-V PCML J41 Transceiver transmit channel

HSMC_TX_N4

1.4-V PCML J42 Transceiver transmit channel

HSMC_TX_P5

1.4-V PCML K39 Transceiver transmit channel

HSMC_TX_N5

1.4-V PCML K40 Transceiver transmit channel

HSMC_TX_P6

1.4-V PCML H39 Transceiver transmit channel

HSMC_TX_N6

1.4-V PCML H40 Transceiver transmit channel

HSMC_TX_P7

1.4-V PCML G41 Transceiver transmit channel

HSMC_TX_N7

1.4-V PCML G42 Transceiver transmit channel

HSMC_D0

2.5-V BB9 Dedicated CMOS I/O bit 0

HSMC_D1

2.5-V AN37 Dedicated CMOS I/O bit 1

HSMC_D2

2.5-V AT11 Dedicated CMOS I/O bit 2

HSMC_D3

2.5-V BD8 Dedicated CMOS I/O bit 3

JTAG_TCK

2.5-V AL34 JTAG clock

JTAG_FPGA2_TDO

2.5-V AL36 JTAG data input

HSMC_JTAG_TDO

2.5-V — JTAG data output

Table 2–22. HSMC Port Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)

Board

Reference

(J1)

Schematic Signal Name I/O Standard

Stratix V GX

FPGA2 Device Pin

Number

Description

1 2 ... 44 45 46 47 48 49 50 51 52 53 54 ... 83 84

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Altera Stratix V Advanced Systems Development Board Instrukcja Użytkownika Strona 49

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