Altera Stratix V Advanced Systems Development Board Instrukcja Użytkownika Pobierz pdf (Strona 68)

2–58 Chapter 2: Board Components

Memory

Stratix V Advanced Systems Development Board January 2014 Altera Corporation

Reference Manual

MoSys MSR576

Each FPGA on the development board supports a 576-Mb MoSys MSR576 Bandwidth

Engine SRAM interface for very-high-speed sequential memory access. The 16-bit

transceiver based interface can run up to 10.3125 G per channel, which encapsulates

four SRAM memory interfaces internally, each with a 2Mx72 configuration. Each

interface supports up to 18.6 GB/s read memory bandwidth.

Table 2–27 lists the MoSys MSR576 interface pin assignments, signal names, and

functions relative to the Stratix V GX FPGAs.

QVLD

— ————Read data valid (Unused)

RPSN

1.5-V HSTL Class I AT18 AJ10 B32 V33 Read port select

WPSN

1.5-V HSTL Class I AP16 AL11 A34 N31 Write port select

Table 2–26. FPGA2 QDRII+ Pin Assignments, Signal Names and Functions (Part 3 of 3)

Board

Reference

Schematic

Signal Name

I/O Standard

Stratix V GX FPGA Device Pin Number

Description

QDR2E QDR2F QDR2G QDR2H

Table 2–27. MoSys MSR576 Interface Pin Assignments, Signal Names and Functions (Part 1 of 5)

Board Reference Schematic Signal Name I/O Standard

Stratix V GX FPGA

Device Pin Number

Description

FPGA1 MoSys (U4)

G20

MOSYS1_AMON_0

1.5-V CMOS — Analog monitor

MOSYS1_AMON_1

1.5-V CMOS — Analog monitor

P22

MOSYS1_CLKDIVIDE

1.5-V CMOS B16 REFCLK divider enable

A21

MOSYS1_CMDARX_N0

1.4-V PCML AY5 Transceiver output

C20

MOSYS1_CMDARX_N1

1.4-V PCML AV5 Transceiver output

A19

MOSYS1_CMDARX_N2

1.4-V PCML AU3 Transceiver output

C18

MOSYS1_CMDARX_N3

1.4-V PCML AT5 Transceiver output

A17

MOSYS1_CMDARX_N4

1.4-V PCML AR3 Transceiver output

C16

MOSYS1_CMDARX_N5

1.4-V PCML AN3 Transceiver output

A15

MOSYS1_CMDARX_N6

1.4-V PCML AL3 Transceiver output

C14

MOSYS1_CMDARX_N7

1.4-V PCML AJ3 Transceiver output

B21

MOSYS1_CMDARX_P0

1.4-V PCML AY6 Transceiver output

D20

MOSYS1_CMDARX_P1

1.4-V PCML AV6 Transceiver output

B19

MOSYS1_CMDARX_P2

1.4-V PCML AU4 Transceiver output

D18

MOSYS1_CMDARX_P3

1.4-V PCML AT6 Transceiver output

B17

MOSYS1_CMDARX_P4

1.4-V PCML AR4 Transceiver output

D16

MOSYS1_CMDARX_P5

1.4-V PCML AN4 Transceiver output

B15

MOSYS1_CMDARX_P6

1.4-V PCML AL4 Transceiver output

D14

MOSYS1_CMDARX_P7

1.4-V PCML AJ4 Transceiver output

A11

MOSYS1_CMDBRX_N0

1.4-V PCML AG3 Transceiver output

C10

MOSYS1_CMDBRX_N1

1.4-V PCML AE3 Transceiver output

MOSYS1_CMDBRX_N2

1.4-V PCML AC3 Transceiver output

1 2 ... 63 64 65 66 67 68 69 70 71 72 73 ... 83 84

Komentarze do niniejszej Instrukcji

Brak uwag

Altera Stratix V Advanced Systems Development Board Instrukcja Użytkownika Strona 68

Komentarze do niniejszej Instrukcji

Powiązane produkty i podręczniki dla Urządzenia pomiarowe Altera Stratix V Advanced Systems Development Board