Altera Stratix V Advanced Systems Development Board Instrukcja Użytkownika Pobierz pdf (Strona 63)

Chapter 2: Board Components 2–53

Memory

January 2014 Altera Corporation Stratix V Advanced Systems Development Board

Reference Manual

DQ63

1.5-V SSTL Class I BB29 C13 Data bus

DQS_P0

Differential 1.5-V

SSTL Class I

AY30 D21 Data strobe

DQS_N0

Differential 1.5-V

SSTL Class I

BA29 D20 Data strobe

DQS_P1

Differential 1.5-V

SSTL Class I

AE27 H21 Data strobe

DQS_N1

Differential 1.5-V

SSTL Class I

AE28 H20 Data strobe

DQS_P2

Differential 1.5-V

SSTL Class I

AL30 V21 Data strobe

DQS_N2

Differential 1.5-V

SSTL Class I

AL31 V20 Data strobe

DQS_P3

Differential 1.5-V

SSTL Class I

AJ25 T20 Data strobe

DQS_N3

Differential 1.5-V

SSTL Class I

AJ26 T19 Data strobe

DQS_P4

Differential 1.5-V

SSTL Class I

AR27 L15 Data strobe

DQS_N4

Differential 1.5-V

SSTL Class I

AR28 K14 Data strobe

DQS_P5

Differential 1.5-V

SSTL Class I

AK30 V17 Data strobe

DQS_N5

Differential 1.5-V

SSTL Class I

AL29 U17 Data strobe

DQS_P6

Differential 1.5-V

SSTL Class I

AT26 Y16 Data strobe

DQS_N6

Differential 1.5-V

SSTL Class I

AU26 W16 Data strobe

DQS_P7

Differential 1.5-V

SSTL Class I

BC28 E15 Data strobe

DQS_N7

Differential 1.5-V

SSTL Class I

BD28 D15 Data strobe

ODT

1.5-V SSTL Class I AF34 L18 On-die termination enable

RASN

1.5-V SSTL Class I AN33 J19 Row address strobe

RESETN

1.5-V SSTL Class I AE30 R19 Reset

WEN

1.5-V SSTL Class I AP33 H16 Write enable

ZQ01

— — — ZQ impedance calibration

ZQ02

— — — ZQ impedance calibration

ZQ03

— — — ZQ impedance calibration

ZQ04

— — — ZQ impedance calibration

Table 2–24. FPGA2 DDR3 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 6 of 6)

Board

Reference

Schematic

Signal Name

I/O Standard Stratix V GX FPGA2 Device Pin Number Description

1 2 ... 58 59 60 61 62 63 64 65 66 67 68 ... 83 84

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