Altera Stratix V Advanced Systems Development Board Instrukcja Użytkownika Pobierz pdf (Strona 53)

Chapter 2: Board Components 2–43

Memory

January 2014 Altera Corporation Stratix V Advanced Systems Development Board

Reference Manual

1.5-V SSTL Class I BD22 B26 Address bus

A10

1.5-V SSTL Class I AU20 A28 Address bus

A11

1.5-V SSTL Class I BC22 D27 Address bus

A12

1.5-V SSTL Class I AW20 F28 Address bus

A13

1.5-V SSTL Class I AT21 E27 Address bus

BA0

1.5-V SSTL Class I BA21 F29 Bank address bus

BA1

1.5-V SSTL Class I BD20 P26 Bank address bus

BA2

1.5-V SSTL Class I AU21 B28 Bank address bus

CASN

1.5-V SSTL Class I AK20 A29 Column address strobe

CKE

1.5-V SSTL Class I AT20 H29 Clock enable

CLK_N

Differential 1.5-V

SSTL Class I

AW22 H26 Differential output clock

CLK_P

Differential 1.5-V

SSTL Class I

AV22 J27 Differential output clock

CSN

1.5-V SSTL Class I BB21 E29 Chip select

DM0

1.5-V SSTL Class I BB23 D24 Data write mask

DM1

1.5-V SSTL Class I AN22 P29 Data write mask

DM2

1.5-V SSTL Class I AU25 D26 Data write mask

DM3

1.5-V SSTL Class I AL21 U23 Data write mask

DQ0

1.5-V SSTL Class I AT24 E23 Data bus

DQ1

1.5-V SSTL Class I AW23 D23 Data bus

DQ2

1.5-V SSTL Class I AV23 B25 Data bus

DQ3

1.5-V SSTL Class I AU23 E24 Data bus

DQ4

1.5-V SSTL Class I BC23 B23 Data bus

DQ5

1.5-V SSTL Class I BB24 F23 Data bus

DQ6

1.5-V SSTL Class I AY24 A23 Data bus

DQ7

1.5-V SSTL Class I BD23 A25 Data bus

DQ8

1.5-V SSTL Class I AJ21 P27 Data bus

DQ9

1.5-V SSTL Class I AM20 M28 Data bus

DQ10

1.5-V SSTL Class I AJ19 M27 Data bus

DQ11

1.5-V SSTL Class I AM22 N28 Data bus

DQ12

1.5-V SSTL Class I AG19 L26 Data bus

DQ13

1.5-V SSTL Class I AL20 P28 Data bus

DQ14

1.5-V SSTL Class I AG20 N26 Data bus

DQ15

1.5-V SSTL Class I AJ20 R27 Data bus

DQ16

1.5-V SSTL Class I AR25 E26 Data bus

DQ17

1.5-V SSTL Class I AV25 F24 Data bus

DQ18

1.5-V SSTL Class I AW24 F25 Data bus

DQ19

1.5-V SSTL Class I AU24 H24 Data bus

Table 2–23. FPGA1 DDR3 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 7)

Board

Reference

Schematic

Signal Name

I/O Standard Stratix V GX FPGA1 Device Pin Number Description

1 2 ... 48 49 50 51 52 53 54 55 56 57 58 ... 83 84

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