Altera Stratix V Avalon-ST Instrukcja Użytkownika Strona 116
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Setting Up and Verifying MSI Interrupts. Perform them once, during or after enumeration.
1. Disable legacy interrupts by setting Interrupt Disable bit of the Command register using a Configura‐
tion Write Request. The Interrupt Disable bit is bit 10 of the Command register.
2. Enable MSI interrupts by setting the MSI enable of the MSI Control register using a Configuration
Write Request. The MSI enable bit is bit 16 of 0x050.
3. Specify the MSI Address and MSI Data using a Configuration Write Request.
4. Specify the number of MSI vectors in the Multiple Message Enable field of the MSI Control
register using a Configuration Write Request.
5. Select a function and interrupt number using a Configuration Write Request.
6. Set the MSI mask bit for the selected function and interrupt number using a Configuration Write
Request.
7. Generate an MSI interrupt request for the selected function and interrupt number using the app_msi*
interface using a Configuration Write Request. You should receive the MSI Ack. No MSI interrupt
message is sent to the host.
8. Verify that app_msi_status[1:0]=2'b01 when app_msi_ack=1.
9. Read the Pending Bit register for the function specified using a Configuration Read Request. Verify
that the pending bit for the interrupt specified is set to 1.
10.Clear the pending bit using the MSI interrupt interface using a Configuration Write Request.
11.Clear the MSI mask bit for the selected function and interrupt number using a Configuration Write
Request..
12.Verify that the SR-IOV Bridge sends the Message TLP to the host.
13.Read the Pending Bit register of the function specified using a Configuration Read Request. Verify
that the pending bit for the interrupt specified is now 0.
Dropping a Pending MSI Interrupt
The following procedure shows how to drop a pending MSI interrupt. The first four steps are the same as
for Setting Up and Verifying MSI Interrupts Perform them once, during or after enumeration. .
1. Disable legacy interrupts by setting Interrupt Disable bit of the Command register using a Configura‐
tion Write Request. The Interrupt Disable bit is bit 10 of the Command register.
2. Enable MSI interrupts by setting the MSI enable of the MSI Control register using a Configuration
Write Request. The MSI enable bit is bit 16 of 0x050.
3. Set up the MSI Address and MSI Data using a Configuration Write Request.
4. Specify the number of MSI vectors in the Multiple Message Enable field of the MSI Control
register using a Configuration Write Request.
5. Select a function and interrupt number using a Configuration Write Request.
6. Set the MSI mask bit for the selected function and interrupt number using a Configuration Write
Request.
7. Use the MSI interrupt interface (app_msi*) to generate an MSI interrupt request for the selected
Function and interrupt number. You should receive the MSI Ack. No MSI interrupt message is sent to
the host.
8. Verify that app_msi_status[1:0]=2'b01when app_msi_ack=1.
9. Read the Pending Bit register for the function specified using a Configuration Read Request. Verify
that the pending bit corresponding to the interrupt specified is set to 1.
10.Send a Configuration Write Request to clear the pending bit using the MSI interrupt interface.
7-2
Dropping a Pending MSI Interrupt
UG-01097_sriov
2014.12.15
Altera Corporation
Programming and Testing SR-IOV Bridge MSI Interrupts
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- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Example Designs 8
- Debug Features 8
- IP Core Verification 9
- Recommended Speed Grades 10
- Related Information 11
- Subscribe 12
- Qsys Subsystem Description 13
- Parameter Value 15
- Directory Description 16
- Parameter Settings 21
- Parameter Value Description 22
- SR-IOV System Settings 24
- Interrupt Capabilities 27
- Device Capabilities 29
- Error Reporting 30
- Link Capabilities 31
- Slot Capabilities 32
- Power Management 33
- PHY Characteristics 34
- Simulation Options 35
- Avalon-ST TX Interface 37
- Signal Direction Description 38
- Avalon‑ST RX Interface 40
- BAR Hit Signals 43
- Completion Side Band Signals 45
- Signal Directi 46
- Description 46
- Clock Signals 48
- Interrupt Interface 49
- Implementing MSI-X Interrupts 55
- LMI Signals 57
- Serial Data Signals 65
- Test Signals 70
- PIPE Interface Signals 71
- Byte Address 77
- MSI Registers 80
- MSI-X Capability Structure 82
- VF Device ID Register 96
- Page Size Registers 96
- Lane Error Status Register 98
- Bits Register Description 99
- Default Value 99
- Altera Corporation 100
- Registers 100
- Send Feedback 100
- Virtual Function Registers 102
- Name Description 103
- Reset and Clocks 107
- Hard IP for PCI Express 108
- Example Design 108
- UG-01097_sriov 109
- 2014.12.15 109
- Function Level Reset (FLR) 111
- Clock Domains 111
- Clock Summary 114
- Interrupts 115
- Error Handling 118
- Physical Layer Errors 119
- Data Link Layer Errors 119
- Transaction Layer Errors 120
- Error Type Description 121
- Status Bit Conditions 123
- IP Core Architecture 125
- Top-Level Interfaces 126
- Clocks and Reset 126
- Transceiver Reconfiguration 126
- Data Link Layer 127
- Physical Layer 129
- TX Packets 130
- Design Implementation 136
- CONF_DONE 137
- Endpoint Reset 137
- Root Port Reset 137
- SDC Timing Constraints 138
- Debugging 143
- Setting Up Simulation 146
- Use Third-Party PCIe Analyzer 148
- BIOS Enumeration Issues 148
- Address[31:2] 149
- Figure A-6: I/O Read Request 151
- Additional Information 155
- Typographic Conventions 156
- Visual Cue Meaning 157
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