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• ACK/NAK Packets—The ACK/NAK block handles ACK/NAK DLLPs and generates the sequence
number of transmitted packets.
• Transaction Layer Packet Checker—This block checks the integrity of the received TLP and generates
a request for transmission of an ACK/NAK DLLP.
• TX Arbitration—This block arbitrates transactions, prioritizing in the following order:
• Initialize FC Data Link Layer packet
• ACK/NAK DLLP (high priority)
• Update FC DLLP (high priority)
• PM DLLP
• Retry buffer TLP
• TLP
• Update FC DLLP (low priority)
• ACK/NAK FC DLLP (low priority)
Physical Layer
The Physical Layer is the lowest level of the PCI Express protocol stack. It is the layer closest to the serial
link. It encodes and transmits packets across a link and accepts and decodes received packets. The
Physical Layer connects to the link through a high-speed SERDES interface running at 2.5 Gbps for Gen1
implementations, at 2.5 or 5.0 Gbps for Gen2 implementations, and at 2.5, 5.0 or 8.0 Gbps for Gen3
implementations.
The Physical Layer is responsible for the following actions:
• Initializing the link
• Scrambling/descrambling and 8B/10B encoding/decoding for 2.5 Gbps (Gen1), 5.0 Gbps (Gen2), or
128b/130b encoding/decoding of 8.0 Gbps (Gen3) per lane
• Serializing and deserializing data
• Operating the PIPE 3.0 Interface
• Implementing auto speed negotiation (Gen2 and Gen3)
• Transmitting and decoding the training sequence
• Providing hardware autonomous speed control
• Implementing auto lane reversal
UG-01097_sriov
2014.12.15
Physical Layer
9-5
IP Core Architecture
Altera Corporation
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- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Example Designs 8
- Debug Features 8
- IP Core Verification 9
- Recommended Speed Grades 10
- Related Information 11
- Subscribe 12
- Qsys Subsystem Description 13
- Parameter Value 15
- Directory Description 16
- Parameter Settings 21
- Parameter Value Description 22
- SR-IOV System Settings 24
- Interrupt Capabilities 27
- Device Capabilities 29
- Error Reporting 30
- Link Capabilities 31
- Slot Capabilities 32
- Power Management 33
- PHY Characteristics 34
- Simulation Options 35
- Avalon-ST TX Interface 37
- Signal Direction Description 38
- Avalon‑ST RX Interface 40
- BAR Hit Signals 43
- Completion Side Band Signals 45
- Signal Directi 46
- Description 46
- Clock Signals 48
- Interrupt Interface 49
- Implementing MSI-X Interrupts 55
- LMI Signals 57
- Serial Data Signals 65
- Test Signals 70
- PIPE Interface Signals 71
- Byte Address 77
- MSI Registers 80
- MSI-X Capability Structure 82
- VF Device ID Register 96
- Page Size Registers 96
- Lane Error Status Register 98
- Bits Register Description 99
- Default Value 99
- Altera Corporation 100
- Registers 100
- Send Feedback 100
- Virtual Function Registers 102
- Name Description 103
- Reset and Clocks 107
- Hard IP for PCI Express 108
- Example Design 108
- UG-01097_sriov 109
- 2014.12.15 109
- Function Level Reset (FLR) 111
- Clock Domains 111
- Clock Summary 114
- Interrupts 115
- Error Handling 118
- Physical Layer Errors 119
- Data Link Layer Errors 119
- Transaction Layer Errors 120
- Error Type Description 121
- Status Bit Conditions 123
- IP Core Architecture 125
- Top-Level Interfaces 126
- Clocks and Reset 126
- Transceiver Reconfiguration 126
- Data Link Layer 127
- Physical Layer 129
- TX Packets 130
- Design Implementation 136
- CONF_DONE 137
- Endpoint Reset 137
- Root Port Reset 137
- SDC Timing Constraints 138
- Debugging 143
- Setting Up Simulation 146
- Use Third-Party PCIe Analyzer 148
- BIOS Enumeration Issues 148
- Address[31:2] 149
- Figure A-6: I/O Read Request 151
- Additional Information 155
- Typographic Conventions 156
- Visual Cue Meaning 157
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