Altera Stratix V Avalon-ST Instrukcja Użytkownika Strona 32
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Parameter Value Description
Surprise down
reporting
On/Off
When this option is On, a downstream port supports the
optional capability of detecting and reporting the surprise
down error condition. This parameter is only supported for
the Stratix V Hard IP for PCI Express in Root Port mode.
Slot clock
configuration
On/Off When On, indicates that the Endpoint or Root Port uses the
same physical reference clock that the system provides on the
connector. When Off, the IP core uses an independent clock
regardless of the presence of a reference clock on the
connector.
Slot Capabilities
Table 3-8: Slot Capabilities
Parameter Value Description
Use Slot register On/Off The slot capability is required for Root Ports if a slot is implemented
on the port. Slot status is recorded in the PCI Express Capabili-
ties register. This parameter is only supported in Root Port mode.
Defines the characteristics of the slot. You turn on this option by
selecting Enable slot capability. The various bits are defined as
follows:
31 19 18 17 16 15 14
7
6 5
Physical Slot Number
No Command Completed Support
Electromechanical Interlock Present
Slot Power Limit Scale
Slot Power Limit Value
Hot-Plug Capable
Hot-Plug Surprise
Power Indicator Present
Attention Indicator Present
MRL Sensor Present
Power Controller Present
Attention Button Present
04 3 2 1
3-12
Slot Capabilities
UG-01097_sriov
2014.12.15
Altera Corporation
Parameter Settings
Send Feedback
- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Example Designs 8
- Debug Features 8
- IP Core Verification 9
- Recommended Speed Grades 10
- Related Information 11
- Subscribe 12
- Qsys Subsystem Description 13
- Parameter Value 15
- Directory Description 16
- Parameter Settings 21
- Parameter Value Description 22
- SR-IOV System Settings 24
- Interrupt Capabilities 27
- Device Capabilities 29
- Error Reporting 30
- Link Capabilities 31
- Slot Capabilities 32
- Power Management 33
- PHY Characteristics 34
- Simulation Options 35
- Avalon-ST TX Interface 37
- Signal Direction Description 38
- Avalon‑ST RX Interface 40
- BAR Hit Signals 43
- Completion Side Band Signals 45
- Signal Directi 46
- Description 46
- Clock Signals 48
- Interrupt Interface 49
- Implementing MSI-X Interrupts 55
- LMI Signals 57
- Serial Data Signals 65
- Test Signals 70
- PIPE Interface Signals 71
- Byte Address 77
- MSI Registers 80
- MSI-X Capability Structure 82
- VF Device ID Register 96
- Page Size Registers 96
- Lane Error Status Register 98
- Bits Register Description 99
- Default Value 99
- Altera Corporation 100
- Registers 100
- Send Feedback 100
- Virtual Function Registers 102
- Name Description 103
- Reset and Clocks 107
- Hard IP for PCI Express 108
- Example Design 108
- UG-01097_sriov 109
- 2014.12.15 109
- Function Level Reset (FLR) 111
- Clock Domains 111
- Clock Summary 114
- Interrupts 115
- Error Handling 118
- Physical Layer Errors 119
- Data Link Layer Errors 119
- Transaction Layer Errors 120
- Error Type Description 121
- Status Bit Conditions 123
- IP Core Architecture 125
- Top-Level Interfaces 126
- Clocks and Reset 126
- Transceiver Reconfiguration 126
- Data Link Layer 127
- Physical Layer 129
- TX Packets 130
- Design Implementation 136
- CONF_DONE 137
- Endpoint Reset 137
- Root Port Reset 137
- SDC Timing Constraints 138
- Debugging 143
- Setting Up Simulation 146
- Use Third-Party PCIe Analyzer 148
- BIOS Enumeration Issues 148
- Address[31:2] 149
- Figure A-6: I/O Read Request 151
- Additional Information 155
- Typographic Conventions 156
- Visual Cue Meaning 157
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