Altera Unique Chip ID Instrukcja Użytkownika Pobierz pdf (Strona 10)

Figure 7: Simulation in Quartus II Design Flow

Post-fit timing

simulation netlist

Post-fit timing

simulation (3)

Post-fit functional

simulation netlist

Post-fit functional

simulation

Analysis & Synthesis

Fitter

(place-and-route)

TimeQuest Timing Analyzer

Device Programmer

Quartus II

Design Flow

Gate-Level Simulation

Post-synthesis

functional

simulation

Post-synthesis functional

simulation netlist

(Optional) Post-fit

timing simulation

RTL Simulation

Design Entry

(HDL, Qsys, DSP Builder)

Altera Simulation

Models

EDA

Netlist

Writer

Post-fit timing simulation is not supported for 28nm and later device archetectures. Altera IP supports

a variety of simulation models, including simulation-specific IP functional simulation models and

Note:

encrypted RTL models, and plain text RTL models. These are all cycle-accurate models. The models

support fast functional simulation of your IP core instance using industry-standard VHDL or Verilog

HDL simulators. For some cores, only the plain text RTL model is generated, and you can simulate

that model. Use the simulation models only for simulation and not for synthesis or any other purposes.

Using these models for synthesis creates a nonfunctional design.

Related Information

Simulating Altera Designs

Ports

Figure 8: ALTCHIP_ID Ports

ALTCHIP_ID

clkin

data_valid

chip_id[63..0]

reset

Altera Unique Chip ID IP Core User Guide

Altera Corporation

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Ports

2014.09.02

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