Altera GPIO Instrukcja Użytkownika

Altera GPIO IP Core User Guide2014.08.18ug-altera_gpioSubscribeSend FeedbackThe Altera GPIO megafunction IP core supports General Purpose I/O (GPIO) c

Signal Name Direction Descriptionpad_in[SIZE -1:0] Input Input pad port only when the input path is used.pad_in_b[SIZE -1:0] Input Input negative pad

Signal Name Direction Descriptionoe[OE_SIZE - 1 : 0] Input OE connection from the core to the Altera GPIOIP core when in bidirectional mode or in outp

Clock Interface SignalsSignal Name Direction Descriptionck Input This clock feeds a packed register or DDIO in input and outputpaths when half-rate DD

Data Interface Signals and Corresponding ClocksThe following table shows the data interface signals and the corresponding clocks.Table 3: Data Interfa

Signal Name Configuration Clocksclr/sset/ all pad signalsRegister Mode: SimpleRegister/DDIOckHalf rate: not usedSeparate Clocks: offRegister Mode: DDI

Altera GPIO Timing ComponentsThe following paths are the timing components for Altera GPIO IP core:• I/O interface paths (from FPGA to external receiv

Figure 9: Timing Components in the Altera GPIO Output PathPADACLR_NAPRE_NDATAOUT[0]DATAOUT[2]DATAOUT[1]DATAOUT[3]CLK_HRCLK_FRDDIOOUTDDIOOUTDDIOOUTDela

Related Information• AN 433: Constraining and Analyzing Source-Synchronous InterfacesDescribes techniques for constraining and analyzing source-synchr

DDIO Input Register (Full-Rate or Half-Rate)Figure 12: DDIO Input Register (Full-Rate or Half-Rate)Outside FPGAFPGAThe input side of full-rate and hal

Note: The CLK_HR frequency must be half the frequency of CLK_FR. If the clocks are driven by IOPLL,you may consider using the derive_pll_clocks SDC co

Migrating Your IPTo use the IP migration flow:1. Open your ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, or ALTIOBUF IP in the IPParameter Editor.2. In the

set_output_delayThese commands instruct the TimeQuest Timing Analyzer to timing analyze the positive data and thenegative data against the output cloc

mode. The Fitter will attempt to configure the IOPLL for a better setup and hold slack of the input I/Otiming analysis.For the output and output enabl

To generate simulation design example for a VHDL-only simulator, run the following script:quartus_sh -t make_sim_design.tcl VHDLThis script generates

Name Values DescriptionData width 1 to 128 Specifies the data width.Use legacy top-level port names Turn on, Turn off Reverts to ports used in Arria V

Name Values DescriptionSeparate input/output Clocks Turn on, Turn off Allows the Altera GPIO to use separate clocks forinput and output data paths.Ove

Note: The Altera GPIO megafunction does not support dynamic calibration of the input path. Forapplications requiring dynamic calibration of the input

Figure 3: Input Path WaveformThe pad receives data. DDIO IN (1) (refer to Figure 2) captures data on the rising and falling edges ofCLK_FR, and sends

Figure 4: Output Path (Simplified View)PADACLR_NAPRE_NDATAOUT[0]DATAOUT[2]DATAOUT[1]DATAOUT[3]CLK_HRCLK_FRDDIOOUTDDIOOUTDDIOOUTDelayElementHR FROEfrom

Output Path WaveformThe waveform for the output path is similar to Figure 3.OE PathThe following figure shows the simplified view of a GPIO OE path.Fi

The following table lists the Altera GPIO IP core main interfaces:Table 2: Altera GPIO IP Core InterfacesInterface DescriptionPad Interface Connects t