Altera ALTDQ_DQS2 Instrukcja Użytkownika

ALTDQ_DQS2 IP Core User Guide2014.12.17UG-01089SubscribeSend FeedbackThe Altera ALTDQ_DQS2 megafunction IP core controls the double data rate (DDR) I/

Figure 7: Upgrading IP CoresDisplays upgrade status for all IP coresin the ProjectUpgrades all IP core that support “Auto Upgrade”Upgrades individual

Date Version ChangesDecember 2012 2.0 • Updated “ALTDQ_DQS2 Ports” on page 3–10:• Major update to Figure 3–8 on page 3–10 toclearly define the device

Related InformationAltera IP Release NotesALTDQ_DQS2 Parameter SettingsYou can instantiate and parameterize using the IP Catalog and parameter editor

Parameter Editor GUI SettingCLI ParameterDescriptionNameLegal ValuesNameLegalValues(1)Memory frequency 1–1068INPUT_FREQ 120–1068This setting specifies

Parameter Editor GUI SettingCLI ParameterDescriptionNameLegal ValuesNameLegalValues(1)Use dynamicconfiguration scanchains—USE_DYNAMIC_CONFIGtruefalseT

Parameter Editor GUI SettingCLI ParameterDescriptionNameLegal ValuesNameLegalValues(1)Capture StrobeCapture strobetypeSingleDifferentialComplemen‐tary

Parameter Editor GUI SettingCLI ParameterDescriptionNameLegal ValuesNameLegalValues(1)Treat the capturestrobe enable as ahalf-rate signal—USE_HALF_RAT

Parameter Editor GUI SettingCLI ParameterDescriptionNameLegal ValuesNameLegalValues(1)Use reset signal tostop output strobe—USE_OUTPUT_STROBE_RESETtru

Parameter Editor GUI SettingCLI ParameterDescriptionNameLegal ValuesNameLegalValues(1)Preamble type highlownonePREAMBLE_TYPEhighlownoneThis setting se

Figure 8: DQ and DQS Input Paths for Stratix V Devicescapture_strobe_enaPREDQINLOstrobe_ena_clock_inDQS Enable ControlDQS Delay ChainHIDQSINDQSBUSOUTI

Figure 9: Data Input Path for Arria V, Cyclone V, and Stratix V DevicesDATAINDelayChainDDIOInFIFO REN LogicDATAOUT[0]DATAOUT[1]DATAOUT[2]DATAOUT[3]HR

Resource Utilization and PerformanceTo view the compilation reports in the Quartus II software, follow these steps:1. On the Processing menu, click St

DQS LogicThe DQS input path in Arria V and Cyclone V devices has the following differences from Stratix V andearlier versions of the device families:•

pointers. For protocols using a bidirectional strobe, the write enable signal is tied to VCC and DQSgating/ungating implements the write enable functi

The determination of the correct latencies to implement at each of these FIFOs is important and cannotbe done during compilation. When you attempt to

The following figure shows the DQ and DQS output path for additional DQ pins usage, where y = 0 to(m-1) and m= the number of DQ pinsFigure 13: DQ and

Block Name DescriptionDDR output registers Represents the DDIO registers that transfer DDR signalsfrom the core to the DQ/DQS pins.Related Information

Figure 15: ALTDQ_DQS2 Block Diagram by Port Types-ALTDQ_DQS2config_clock_in config_data_in config_dqs_ena config_dqs_io_ena config_update core_clock_i

ALTDQ_DQS2 Data Strobe PortsTable 6: ALTDQ_DQS2 Data Strobe PortsPort Name Type Width Descriptioncapture_strobe_enaInput 1 Controls the DQS enable con

Port Name Type Width Descriptionoutput_strobe_enaInput 2 = half-rate1 = full-rateThe gating signal for theoutput_strobe_out port.This port is supporte

Port Name Type Width Descriptionstrobe_ena_hr_clock_inInput 1 Receives the clock signal fromthe clock pin or the PLL to clockthe DQS enable control bl

ALTDQ_DQS2 Data PortsThe following table lists the ALTDQ_DQS2 data ports where n= number of DQ pins, m= number ofadditional output-only DQ pins, x = 0

IP Catalog and Parameter Editor (replaces MegaWizard Plug-In Manager)The Quartus II IP Catalog (Tools > IP Catalog) and parameter editor help you e

Port Name Type Width(2)Descriptionread_data_out[]Output 2n = full-rate4n = half-rateSends the captured data from theexternal device to the core.This p

Port Name Type Width(2)Descriptionwrite_data_out[]Output n Sends the DDR data signal to theexternal device. For example,data to be written to the exte

ALTDQ_DQS2 Termination Control PortsTable 8: ALTDQ_DQS2 Termination Control PortsPort name Type Width Descriptionparallelterminationcontrol_in[]Input

ALTDQ_DQS2 PLL and DLL PortsTable 9: ALTDQ_DQS2 PLL and DLL PortsPort name Type Width Descriptiondll_delayctrl_in[]Input 7 Receives the 7-bit delay se

ALTDQ_DQS2 Hard FIFO PortsTable 10: Hard FIFO PortsPorts Type Width Descriptionlfifo_rdata_en_fullInput 2 Data input to the latency shifterFIFO. This

Ports Type Width Descriptionvfifo_qvldInput Arria V andCyclone Vdevices: 2Stratix Vdevices: 1Data input to the data validFIFO. This signal is the full

Table 11: ALTDQ_DQS2 Dynamic Configuration PortsPort name Type Width Descriptionconfig_clock_inInput 1 The ALTDQ_DQS2 dynamicconfiguration interface c

Port name Type Width Descriptionconfig_dqs_io_enaInput 1 An input port that controls theenable input on the DQS I/Oconfigurations. Receives theclock e

Port name Type Width Descriptionconfig_data_inInput 1 Receives the serial configurationdata stream that shifts into theserial-to-parallel shift regist

Figure 17: Reconfiguration Scan ChaindinupdateenableclkDQ0dinupdateenableclkDQ1dinupdateenableclkDQSconfig_dataconfig_updateconfig_clock_inconfig_io_e

available in the Quartus II IP Catalog. For more information about using the Qsys IP Catalog, referto Creating a System with Qsys in the Quartus II Ha

I/O Configuration Block Bit Sequence for Arria V GZ and Stratix V DevicesFigure 18: I/O and DQS Delay Chains for Arria V GZ and Stratix V Devices10DQD

Legendin Figure18BitBit Name DescriptionB 11..6 padtoinputregisterrisefalldelaysetting Connects to the delayctrlin port ofthe second D1 delay chain to

Table 13: I/O Configuration Block Bit Value for Arria V GZ and Stratix V DevicesBitBit Name/BitDefault Value(Binary)Min.ValueMax.ValueInc. Value5..0 p

Table 14: DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V DevicesLegend in I/O Configu‐ration Block BitSequence for Arria VGZ and St

Legend in I/O Configu‐ration Block BitSequence for Arria VGZ and Stratix VDevices on page 40Bit Bit Name DescriptionH 23..18 octdelaysetting2 Connects

Legend in I/O Configu‐ration Block BitSequence for Arria VGZ and Stratix VDevices on page 40Bit Bit Name DescriptionK 33..32 dqoutputphasesetting Conn

Legend in I/O Configu‐ration Block BitSequence for Arria VGZ and Stratix VDevices on page 40Bit Bit Name DescriptionN 45 postamblephaseinvert Connects

Legend in I/O Configu‐ration Block BitSequence for Arria VGZ and Stratix VDevices on page 40Bit Bit Name DescriptionP 69 enaoctphasetransferreg Connec

Legend in I/O Configu‐ration Block BitSequence for Arria VGZ and Stratix VDevices on page 40Bit Bit Name DescriptionT 88..87 dqsinputphasesetting Conn

Legend in I/O Configu‐ration Block BitSequence for Arria VGZ and Stratix VDevices on page 40Bit Bit Name DescriptionX 96..94 enaoutputcycledelaysettin

In the following list of search locations, a recursive descent is annotated by **. A single * signifies any file.Table 1: IP Search LocationsLocation

Bit Bit Name Default Value (Binary) MinValueMax Value Inc. Unit29..28 dqsoutputphasesetting 0 00 = 0°01 = 45°10 = 90°11 = 135°30 dqsoutputpowerdown 1

Bit Bit Name Default Value (Binary) MinValueMax Value Inc. Unit65..46 dqs2xoutputphasesettingdqs2xoutputpowerdowndqs2xoutputphaseinvertdq2xoutputphase

Bit Bit Name Default Value (Binary) MinValueMax Value Inc. Unit88..87 dqsinputphasesetting 0 00 = 0°01 = 45°10 = 90°11 = 135°89 enadqsphasetransferreg

I/O Configuration Block Bit Sequence for Arria V and Cyclone V DevicesFigure 19: I/O and DQS Delay Chains for Arria V and Cyclone V Devices4Open Drain

Table 16: I/O Configuration Block Bit Sequence for Arria V and Cyclone V DevicesLegend in Figure 19 Bit External Bit Name DescriptionA 4..0 padtoinput

Legend in Figure 19 Bit External Bit Name DescriptionD 17..15 readfifomode Connects to the dynfifomodeport of input register readFIFO block. The read

Bit Bit Name DefaultValue(Binary)Min. Value Max. Value Inc. Value17..15 readfifomode 0 000: Half-rate Read FIFO Mode001: Full-rate Read FIFO Mode010:

Legend in Figure 19 Bit Bit Name DescriptionH 9..5 dqsenablegatingdelaysetting Connects to the delayctrlin portof the postamble T11 delaychain (gated)

Legend in Figure 19 Bit Bit Name DescriptionM 22 postamblephaseinvert Connects to the phaseinvertctrlport of the clock phase selectblock to select bet

Bit External Bit Name Default Value(Binary)Min. Value Max. Value Inc. Value21..17 dqsbusoutdelaysetting 0 intrinsic delay 775 ps +intrinsic delay25 ps

Note: If you add a component to the search path, you must refresh your system by clicking File > Refreshto update the IP Catalog.Specifying IP Core

Instantiating ALTDQ_DQS2 IP CoreTo instantiate the ALTDQ_DQS2 IP core, perform the following steps:1. In the Quartus II software, open the Top_SV_13.0

Instantiating the ALTDLL IP CoreTo instantiate the ALTDLL IP core, follow these steps:1. In the IP Catalog (Tools > IP Catalog), locate and double-

Figure 23: ALT_OCT Parameter Settings Tab4. Click Finish.Instantiating Altera PLL1. In the IP Catalog (Tools > IP Catalog), locate and double-click

Clock Descriptionoutclk_3 125 MHz, used as half-rate clock.outclk_4 500 MHz, used to drive the ALTDLL IP core. The minimum frequency for theALTDLL IP

Figure 26: Simulation Dialog BoxFigure 27: Test Benches Dialog BoxFigure 28: Edit Test Bench Settings Dialog Box7. Run Analysis and Synthesis.64Settin

8. To view the simulation results, on the Tools menu, select Run Simulation Tool and then click RTLSimulation.For a successful simulation, you may nee

Figure 30: Pin Planner10.Run the Fitter, Timing Analysis, and Assembler. An SDC example (top.sdc) is included in the exampledesign.Related Information

Component DescriptionDQS Agent• Acts as an external memory device.• Has a side channel (side reads/writes) communicating directly with theDQS driver,

18.675 us, the enable_driver signal is asserted to specify that the internal calibration is completed. TheDQS driver, which acts as the host controlle

Figure 33: DQS Write Operation WaveformNote: Before and after the DQS write operation, the dq signal is in Hi-Z mode to filter any unwantedglitch on t

Figure 5: IP Parameter EditorView IP portand parameter detailsApply preset parameters forspecific applicationsSpecify your IP variation nameand target

The following figure shows the waveform for the side write operation.Figure 36: Side Write Operation WaveformNote: The incoming data at dq is edge-ali

Figure 38: DQS Delay Chain WaveformHowever, when you enable the dynamic configuration feature, phasectrlin (which is set via thedqsinputphasesetting p

Figure 40:Hardened in ALTDQ_DQS2 Megafunction.ReadFIFO DOUT DINREN WRENLatencyShifterFIFODataValidFIFOData to Core Data from DQTo DQS EnableRead Data

the write address counter, while the re signal controls when to advance the readaddress counter.When the read/write address pointers are the same, wri

set_input_delay -clock {virtual_dqs_in} -min -add_delay -0.300[get_ports{read_write_data_io[*]}]set_input_delay -clock {virtual_dqs_in} -clock_fall -m

Example 3: set_multicycle_path Commandsset_multicycle_path -rise_from [get_clocks {virtual_dqs_in}] -rise_to[get_clocks {dqs_in}] -setup -end 0set_mul

Figure 44:The following set_false_path commands ensure that we are analyzing only the same edgetransfers, by removing the opposite edge transfers.Note

altdq_dqs2_stratixv:altdq_dqs2_inst/input_path_gen[*].read_fifo_hr�INPUT_DFF_*} -setup -end 0set_multicycle_path -from {*/altdq_dqs2_stratixv:altdq_dq

Figure 45: ALTDQ_DQS2 Parameter Settings for Arria V Devices5. Click Finish.Note:Because your design requires bidirectional strobe, you must use the D

Figure 46: ALTDLL Parameter Settings4. Click Finish.Instantiating ALT_OCT IP Core1. In the IP Catalog (Tools > IP Catalog), locate and double-click

Figure 6: IP Core Generated FilesNotes:1. If supported and enabled for your IP variation2. If functional simulation models are generated<Project Di

Instantiating Altera PLL1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.The parameter edito

Clock Descriptionoutclk_4 200 MHz. Used to drive the ALTDLL IP core. The following are the ALTDLLminimum frequency:• Arria V devices: 200 MHZ• Arria V

Figure 50: Simulation Dialog BoxFigure 51: Test Benches Dialog BoxFigure 52: Edit Test Bench Settings Dialog Box7. Run Analysis and Synthesis.82Settin

8. To view the simulation results, on the Tools menu, select Run Simulation Tool and then click RTLSimulation.For a successful simulation, you may nee

Figure 54: Pin Planner10.Run the Fitter, Timing Analysis, and Assembler. An SDC example (top.sdc) is included in the exampledesign.Related Information

Component DescriptionDQS Agent• Acts as an external memory device.• Has a side channel (side reads/writes) communicating directly with theDQS Driver,

Dynamic ConfigurationAt 100 ns, there is a high pulse on the beginscan signal. When the agent_output_enable signal is pulledlow, the strobe_io and age

The following figure shows the DQS write operation waveform.Figure 57: DQS Write Operation WaveformNote: Before and after the DQS write operation, the

Figure 59: Side Read Operation WaveformSide Write OperationThe side write operation begins between 9.185 µs and 9.255 µs. The data written out from th

Figure 61: DQS Read Operation WaveformAs the incoming data arrives at the ALTDQ_DQS2 IP core, the edge-aligned data onread_write_data_io, and strobe o

Table 2: IP Core Upgrade StatusIP Core Status Corrective ActionRequired Upgrade IPComponentsYou must upgrade the IP variation before compiling in the

Figure 63: VFIFO, LFIFO and Read FIFO in Arria V and Cyclone V DevicesReadFIFO DOUT DINREN WRENLatencyShifterFIFODataValidFIFOData to Core Data from D

Figure 64:Note: The write enable (we) and read enable (re) signals of the hard read FIFO are different from thewrreq and rdreq signals of the DCFIFO.

Figure 65: Simulation ResultsSDC WalkthroughTo create a new .sdc, follow these steps:1. Constrain the clocks coming into the FPGA with the create_cloc

Figure 66:Analyzing Same Edge TransferThe following set_false_path commands ensure that you are analyzing only the same edge transfers, byremoving the

Constraining Outgoing DQS StrobeThe design sends the data out by a clock shifted 270° so that the non-shifted clock is center-aligned. Theseconstraint

The following set_false_path commands ensure that we are analyzing only the same edgetransfers, by removing the opposite edge transfers.Note: These as

• Functional Description—UniPHYFor more information on some basic calibration.tq_analysis.tclThe tq_analysis.tcl is a script that analyzes specific dq

--component-param=USE_OUTPUT_STROBE=”False” --component-param=DQS_PHASE_SETTING=”3”This command generates two files—my_dqdqs2.v and my_dqdqs2_altdq_dq

Date Version ChangesJuly 2014 2014.07.07• Replaced MegaWizard Plug-In Managerinformation with IP Catalog.• Added standard information aboutupgrading I

Date Version ChangesDecember 2012 2.0 • Major enhancement to include:• Arria V and Cyclone V devices information.• Updated “Features” on page 1–1:• In