Altera Unique Chip ID Instrukcja Użytkownika Pobierz pdf (Strona 11)

Table 2: ALTCHIP_ID Ports

DescriptionSize (in Bit)I/OPort

Feeds clock signal to the chip ID block. The

maximum supported frequency is 100 MHz.

When you provide a clock signal, the IP core

reads the value of the unique chip ID and

sends the value to the chip_id output port.

1Inputclkin

Resets the IP core when you assert high to

the reset signal for at least one clock cycle.

The chip_id [63:0]output port holds the

value of the unique chip ID until you

reconfigure the device or reset the IP core.

1Inputreset

Indicates that the unique chip ID is ready for

retrieval. If the signal is low, the IP core is in

initial state or in progress to load data from

a fuse ID. After the IP core asserts the signal,

the data is ready for retrieval at the chip_

id[63..0] output port.

1Outputdata_valid

Indicates the unique chip ID according to its

respective fuse ID location. The data is only

valid after the IP core asserts the data_valid

signal.

The value at power-up resets to 0.

64Outputchip_id

Resetting the ALTCHIP_ID IP Core

To reset the ALTCHIP_ID IP core, you must assert high to the reset signal for at least one clock cycle. After

you deassert the reset signal, the ALTCHIP_ID IP core rereads the unique chip ID from the fuse ID block.

The ALTCHIP_ID IP core asserts the data_valid signal after completing the operation.

Document Revision History

The following table lists the revision history for this document.

Table 3: Date Version Changes

ChangesVersionDate

• Updated document title to reflect new name of "Altera Unique

Chip ID" IP core.

2014.09.02September, 2014

Altera Corporation

Altera Unique Chip ID IP Core User Guide

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