Altera Video and Image Processing Suite Instrukcja Użytkownika Strona 119
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Signal Direction Description
dout_N_ready Input dout_N port Avalon-ST ready signal. The downstream
device asserts this signal when it is able to receive data.
dout_N_startofpacket Output dout_N port Avalon-ST startofpacket signal. This signal
marks the start of an Avalon-ST packet.
dout_N_valid Output dout_N port Avalon-ST valid signal. The IP core asserts
this signal when it produces data.
Video Mixing Control Registers
For efficiency reasons, the Video and Image Processing Suite IP cores buffer a few samples from the input
stream even if they are not immediately processed. This implies that the Avalon-ST inputs for foreground
layers assert ready high, and buffer a few samples even if the corresponding layer has been deactivated.
Table 6-6: Alpha Blending Mixer Control Register Map
The table below describes the control register map for Alpha Blending Mixer IP core.
Address Register Description
0 Control Bit 0 of this register is the Go bit, all other bits are unused.
Setting this bit to 0 causes the IP core to stop the next time
control information is read.
1 Status Bit 0 of this register is the Status bit, all other bits are unused.
2 Layer 1 X Offset in pixels from the left edge of the background layer to
the left edge of layer 1.
3 Layer 1 Y Offset in pixels from the top edge of the background layer to
the top edge of layer 1.
4 Layer 1 Active
• If set to 0—data from the input stream is not pulled out.
• If set to 1—layer 1 is displayed.
• If set to 2—data in the input stream is consumed but not
displayed. The IP core still propagates the Avalon-ST
packets of type 2 to 14 as usual.
The value of this register is checked at the start of each frame.
If the register is changed during the processing of a video
frame, the change does not take effect until the start of the
next frame.
5 Layer 2 X The rows in the table are repeated in ascending order for each
layer from 1 to the foreground layer...
6-8
Video Mixing Control Registers
UG-VIPSUITE
2015.05.04
Altera Corporation
Video Mixing IP Cores
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Feature Support 7
- Release Information 9
- Device Family Support 10
- IP Core Mode Latency 11
- Interfaces 28
- Video Formats 29
- D0 D1vid_data 32
- Signal Name Description 33
- Avalon-ST Video Protocol 34
- Video Data Packets 38
- Symbol transmitted first 39
- Symbol transmitted last 39
- Plane for even rows 40
- Plane for odd rows 40
- Control Data Packets 42
- Parameters 43
- Description 43
- Type Width Height Interlacin 43
- Order Symbol Order Symbol 45
- Ancillary Data Packets 46
- Packet Propagation 46
- Parameter Name Value 47
- Signal Width Direction 47
- Packet Transfer Examples 48
- Parameter Value 50
- Avalon-MM Slave Interfaces 52
- Avalon-MM Master Interfaces 55
- Related Information 56
- Getting Started 57
- OpenCore Plus IP Evaluation 59
- Control Port 60
- Format Description 61
- Interrupts 64
- Generator Lock 68
- Underflow and Overflow 70
- Timing Constraints 71
- Handling Ancillary Packets 71
- Modules Description 75
- Address Register Description 100
- UG-VIPSUITE 105
- 2015.05.04 105
- 2D FIR Filter IP Core 106
- Coefficient Precision 107
- Parameter Value Description 108
- 2D FIR Filter Signals 109
- Signal Direction Description 110
- Video Mixing IP Cores 112
- Alpha Blending 113
- Video Mixing Signals 116
- 20 Input 3 enable 121
- Chroma Resampler IP Core 122
- 4:4:4 to 4:2:2 123
- 4:2:2 to 4:4:4 123
- Vertical Resampling (4:2:0) 124
- Chroma Resampler Signals 126
- Video Clipping IP Cores 127
- Video Clipping Signals 130
- Color Plane Sequencer IP Core 135
- Rearranging Color Patterns 136
- Splitting and Duplicating 137
- Subsampled Data 138
- Color Plane Sequencer Signals 139
- IP Cores Feature 141
- Input and Output Data Types 142
- Color Space Conversion 142
- Operands 145
- Control Synchronizer IP Core 153
- Control Synchronizer Signals 157
- Deinterlacing IP Cores 160
- Deinterlacing Methods 161
- Bob with Scanline Duplication 162
- Motion-Adaptive 162
- Sobel-Based HQ Mode 164
- Frame Buffering 165
- Types Description 166
- Frame Rate Conversion 167
- Altera Corporation 168
- Send Feedback 168
- Deinterlacing Signals 176
- Register Address 190
- (Decimal) 190
- Register Suggested 190
- Settings 190
- Comments 190
- Tuning Motion Shift 191
- Frame Reader IP Core 192
- Frame Reader Signals 194
- Frame Buffer IP Cores 198
- Double Buffering 199
- Triple Buffering 199
- Locked Frame Rate Conversion 200
- Color Format 201
- Frame Buffer Signals 206
- Gamma Corrector IP Core 214
- Gamma Corrector Signals 215
- Interlacer IP Core 218
- Interlacer Parameter Settings 219
- Interlacer Signals 219
- Interlacer Control Registers 221
- Scaler II IP Core 222
- Bilinear Algorithm 223
- Double-Buffering 226
- Scaler II Parameter Settings 230
- Scaler II Signals 233
- Scaler II Control Registers 235
- Video Switching IP Cores 237
- Mixer Layer Switching 238
- Video Switching Signals 239
- Test Pattern 243
- Trace System IP Core 253
- Trace System Signals 255
- Trace Within System Console 258
- TCL Shell Commands 259
- Command Arguments Function 260
- Packet Visualization 263
- Monitor Settings 264
- Subscribe 269
- Avalon-ST Video Class Library 270
- Class Description 272
- Running the Tests 275
- Video File Reader Test 278
- Example Test Environment 281
- Video Field Life Cycle 282
- Constrained Random Test 283
- Code for Scoreboards 285
- Code for to_grey Function 286
- Complete Class Reference 287
- Method Call Description 288
- Member Description 288
- Raw Video Data Format 299
- Y 410 / A 2R 10 G 10 B 10 301
- Additional Information 306
- Date Version Changes 307
- How to Contact Altera 310
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