Altera Video and Image Processing Suite Instrukcja Użytkownika Strona 97
- Strona / 310
- Spis treści
- BOOKMARKI
Oceniono. / 5. Na podstawie oceny klientów
Address Register Description
7 Total Sample Count The detected sample count of the video streams including
blanking.
8 F0 Total Line Count The detected line count of the video streams F0 field including
blanking.
9 F1 Total Line Count The detected line count of the video streams F1 field including
blanking.
10 Standard The contents of the vid_std signal.
11 SOF Sample Start of frame line register. The line upon which the SOF
occurs measured from the rising edge of the F0 vertical sync.
12 SOF Line SOF line register. The line upon which the SOF occurs
measured from the rising edge of the F0 vertical sync.
13 Refclk Divider Number of cycles of vid_clk (refclk) before refclk_div
signal triggers.
Table 4-21: Clocked Video Input II Registers
Address Register Description
0 Control
• Bit 0 of this register is the Go bit:
• Setting this bit to 1 causes the CVI II IP core to start
data output on the next video frame boundary.
• Bits 3, 2, and 1 of the Control register are the interrupt
enables:
• Setting bit 1 to 1, enables the status update interrupt.
• Setting bit 2 to 1, enables the end of field/frame video
interrupt.
4-38
Clocked Video Interface Control Registers
UG-VIPSUITE
2015.05.04
Altera Corporation
Clocked Video Interface IP Cores
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Feature Support 7
- Release Information 9
- Device Family Support 10
- IP Core Mode Latency 11
- Interfaces 28
- Video Formats 29
- D0 D1vid_data 32
- Signal Name Description 33
- Avalon-ST Video Protocol 34
- Video Data Packets 38
- Symbol transmitted first 39
- Symbol transmitted last 39
- Plane for even rows 40
- Plane for odd rows 40
- Control Data Packets 42
- Parameters 43
- Description 43
- Type Width Height Interlacin 43
- Order Symbol Order Symbol 45
- Ancillary Data Packets 46
- Packet Propagation 46
- Parameter Name Value 47
- Signal Width Direction 47
- Packet Transfer Examples 48
- Parameter Value 50
- Avalon-MM Slave Interfaces 52
- Avalon-MM Master Interfaces 55
- Related Information 56
- Getting Started 57
- OpenCore Plus IP Evaluation 59
- Control Port 60
- Format Description 61
- Interrupts 64
- Generator Lock 68
- Underflow and Overflow 70
- Timing Constraints 71
- Handling Ancillary Packets 71
- Modules Description 75
- Address Register Description 100
- UG-VIPSUITE 105
- 2015.05.04 105
- 2D FIR Filter IP Core 106
- Coefficient Precision 107
- Parameter Value Description 108
- 2D FIR Filter Signals 109
- Signal Direction Description 110
- Video Mixing IP Cores 112
- Alpha Blending 113
- Video Mixing Signals 116
- 20 Input 3 enable 121
- Chroma Resampler IP Core 122
- 4:4:4 to 4:2:2 123
- 4:2:2 to 4:4:4 123
- Vertical Resampling (4:2:0) 124
- Chroma Resampler Signals 126
- Video Clipping IP Cores 127
- Video Clipping Signals 130
- Color Plane Sequencer IP Core 135
- Rearranging Color Patterns 136
- Splitting and Duplicating 137
- Subsampled Data 138
- Color Plane Sequencer Signals 139
- IP Cores Feature 141
- Input and Output Data Types 142
- Color Space Conversion 142
- Operands 145
- Control Synchronizer IP Core 153
- Control Synchronizer Signals 157
- Deinterlacing IP Cores 160
- Deinterlacing Methods 161
- Bob with Scanline Duplication 162
- Motion-Adaptive 162
- Sobel-Based HQ Mode 164
- Frame Buffering 165
- Types Description 166
- Frame Rate Conversion 167
- Altera Corporation 168
- Send Feedback 168
- Deinterlacing Signals 176
- Register Address 190
- (Decimal) 190
- Register Suggested 190
- Settings 190
- Comments 190
- Tuning Motion Shift 191
- Frame Reader IP Core 192
- Frame Reader Signals 194
- Frame Buffer IP Cores 198
- Double Buffering 199
- Triple Buffering 199
- Locked Frame Rate Conversion 200
- Color Format 201
- Frame Buffer Signals 206
- Gamma Corrector IP Core 214
- Gamma Corrector Signals 215
- Interlacer IP Core 218
- Interlacer Parameter Settings 219
- Interlacer Signals 219
- Interlacer Control Registers 221
- Scaler II IP Core 222
- Bilinear Algorithm 223
- Double-Buffering 226
- Scaler II Parameter Settings 230
- Scaler II Signals 233
- Scaler II Control Registers 235
- Video Switching IP Cores 237
- Mixer Layer Switching 238
- Video Switching Signals 239
- Test Pattern 243
- Trace System IP Core 253
- Trace System Signals 255
- Trace Within System Console 258
- TCL Shell Commands 259
- Command Arguments Function 260
- Packet Visualization 263
- Monitor Settings 264
- Subscribe 269
- Avalon-ST Video Class Library 270
- Class Description 272
- Running the Tests 275
- Video File Reader Test 278
- Example Test Environment 281
- Video Field Life Cycle 282
- Constrained Random Test 283
- Code for Scoreboards 285
- Code for to_grey Function 286
- Complete Class Reference 287
- Method Call Description 288
- Member Description 288
- Raw Video Data Format 299
- Y 410 / A 2R 10 G 10 B 10 301
- Additional Information 306
- Date Version Changes 307
- How to Contact Altera 310
Powiązane produkty i podręczniki dla Urządzenia pomiarowe Altera Video and Image Processing Suite
Urządzenia pomiarowe Altera DSP Development Kit, Stratix V Edition Instrukcja Użytkownika
(74 strony)
(74 strony)
Urządzenia pomiarowe Altera Transceiver Signal Integrity Development Kit, Stra Instrukcja Użytkownika
(42 strony)
(42 strony)
Urządzenia pomiarowe Altera Transceiver Signal Integrity Development Kit, Stra Instrukcja Użytkownika
(58 strony)
(58 strony)
Urządzenia pomiarowe Altera Cyclone II EP2C35 PCI Development Board Instrukcja Użytkownika
(50 strony)
(50 strony)
© 2020, manymanuals.pl. Wszelkie prawa zastrzeżone. | 0.050 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Komentarze do niniejszej Instrukcji