Altera Cyclone V SoC Development Board Instrukcja Użytkownika Pobierz pdf (Strona 17)

Chapter 2: Board Components 2–9

MAX V CPLD 5M2210 System Controller

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

FPGA_CONFIG_D13

2.5-V FPGA configuration data

FPGA_CONFIG_D14

2.5-V FPGA configuration data

FPGA_CONFIG_D15

2.5-V FPGA configuration data

FPGA_CVP_CONFDONE

2.5-V FPGA Configuration via Protocol (CvP) done

FPGA_DCLK

2.5-V FPGA configuration clock

FPGA_NCONFIG

2.5-V FPGA configuration active

FPGA_NSTATUS

2.5-V FPGA configuration ready

FPGA_PR_DONE

2.5-V FPGA partial reconfiguration done

FPGA_PR_ERROR

2.5-V FPGA partial reconfiguration error

FPGA_PR_READY

2.5-V FPGA partial reconfiguration ready

FPGA_PR_REQUEST

2.5-V FPGA partial reconfiguration request

B11

HPS_RESETN

2.5-V HPS reset push button

HSMA_PRSNTN

2.5-V HSMC port A present

I2C_SCL_MAX

2.5-V Programmable oscillator I

C clock

I2C_SDA_MAX

2.5-V Programmable oscillator I

C data

JTAG_MAX_TDI

2.5-V JTAG chain data in

JTAG_MAX_TDO

2.5-V JTAG chain data out

JTAG_MAX_TMS

2.5-V JTAG chain mode

JTAG_MUX_TCK

2.5-V JTAG chain clock

P11

M570_CLOCK

1.8-V

25-MHz clock to embedded USB-Blaster II for sending

FACTORY command

M570_PCIE_JTAG_EN

2.5-V M570 JTAG enable for the embedded USB-Blaster II

MAX_AS_CONF

2.5-V

Driven low to enable AS configuration from the EPCQ flash

through U13 to the FPGA

E11

MAX_CONF_DONE

2.5-V Embedded USB-Blaster II configuration done LED

MAX_ERROR

2.5-V FPGA configuration error LED

MAX_FPGA_MISO

2.5-V FPGA to MAX V SPI bus data output

MAX_FPGA_MOSI

2.5-V FPGA to MAX V SPI bus data input

MAX_FPGA_SCK

2.5-V FPGA to MAX V SPI bus clock

MAX_FPGA_SSEL

2.5-V FPGA to MAX V SPI bus slave select

MAX_LOAD

2.5-V FPGA configuration active LED

MAX_RESETN

2.5-V MAX V reset push button

B10

MSEL0

2.5-V FPGA MSEL0 setting

MSEL1

2.5-V FPGA MSEL1 setting

C10

MSEL2

2.5-V FPGA MSEL2 setting

C12

MSEL3

2.5-V FPGA MSEL3 setting

MSEL4

2.5-V FPGA MSEL4 setting

E10

OVERTEMP

2.5-V Temperature monitor fan enable

PCIE_JTAG_EN

2.5-V PCIe JTAG master enable

Table 2–4. MAX V CPLD System Controller Device Pin-Out (Part 3 of 4)

Board

Reference (U19)

Schematic Signal Name I/O Standard Description

1 2 ... 12 13 14 15 16 17 18 19 20 21 22 ... 67 68

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