Altera Cyclone V SoC Development Board Instrukcja Użytkownika Pobierz pdf (Strona 55)

Chapter 2: Board Components 2–47

Memory

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

FLASH_RDYBSYN

1.8-V Ready

FLASH_RESETN

1.8-V Reset

FLASH_WEN

1.8-V Write enable

FLASH_WPN

1.8-V Write protect

FSM_A1

1.8-V Address bus

FSM_A2

1.8-V Address bus

FSM_A3

1.8-V Address bus

FSM_A4

1.8-V Address bus

FSM_A5

1.8-V Address bus

FSM_A6

1.8-V Address bus

FSM_A7

1.8-V Address bus

FSM_A8

1.8-V Address bus

FSM_A9

1.8-V Address bus

FSM_A10

1.8-V Address bus

FSM_A11

1.8-V Address bus

FSM_A12

1.8-V Address bus

FSM_A13

1.8-V Address bus

FSM_A14

1.8-V Address bus

FSM_A15

1.8-V Address bus

FSM_A16

1.8-V Address bus

FSM_A17

1.8-V Address bus

FSM_A18

1.8-V Address bus

FSM_A19

1.8-V Address bus

FSM_A20

1.8-V Address bus

FSM_A21

1.8-V Address bus

FSM_A22

1.8-V Address bus

FSM_A23

1.8-V Address bus

FSM_A24

1.8-V Address bus

FSM_A25

1.8-V Address bus

FSM_A26

1.8-V Address bus

FSM_D0

1.8-V Data bus

FSM_D1

1.8-V Data bus

FSM_D2

1.8-V Data bus

FSM_D3

1.8-V Data bus

FSM_D4

1.8-V Data bus

FSM_D5

1.8-V Data bus

FSM_D6

1.8-V Data bus

FSM_D7

1.8-V Data bus

FSM_D8

1.8-V Data bus

Table 2–36. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)

Board

Reference (U6)

Schematic Signal Name I/O Standard Description

1 2 ... 50 51 52 53 54 55 56 57 58 59 60 ... 67 68

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Altera Cyclone V SoC Development Board Instrukcja Użytkownika Strona 55

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