Altera Cyclone V SoC Development Board Instrukcja Użytkownika Pobierz pdf (Strona 51)

Chapter 2: Board Components 2–43

Memory

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

DDR3_HPS_A9

G26 1.5-V SSTL Class I Address bus

DDR3_HPS_A10

D29 1.5-V SSTL Class I Address bus

DDR3_HPS_A11

C30 1.5-V SSTL Class I Address bus

DDR3_HPS_A12

B30 1.5-V SSTL Class I Address bus

DDR3_HPS_A13

C29 1.5-V SSTL Class I Address bus

DDR3_HPS_A14

H25 1.5-V SSTL Class I Address bus

DDR3_HPS_BA0

E29 1.5-V SSTL Class I Bank address bus

DDR3_HPS_BA1

J24 1.5-V SSTL Class I Bank address bus

DDR3_HPS_BA2

J23 1.5-V SSTL Class I Bank address bus

DDR3_HPS_CASN

E27 1.5-V SSTL Class I Row address select

DDR3_HPS_CKE

L29 1.5-V SSTL Class I Column address select

DDR3_HPS_CLK_P

L23 1.5-V SSTL Class I Differential output clock

DDR3_HPS_CLK_N

M23 1.5-V SSTL Class I Differential output clock

DDR3_HPS_CSN

H24 1.5-V SSTL Class I Chip select

DDR3_HPS_DM2

R28 1.5-V SSTL Class I Write mask byte lane

DDR3_HPS_DM3

W30 1.5-V SSTL Class I Write mask byte lane

DDR3_HPS_DQ16

U26 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ17

T26 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ18

N29 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ19

N28 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ20

P26 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ21

P27 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ22

N27 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ23

R29 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ24

P24 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ25

P25 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ26

T29 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ27

T28 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ28

R27 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ29

R26 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ30

V30 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ31

W29 1.5-V SSTL Class I Data bus

DDR3_HPS_DQS_N2

R18

Differential 1.5-V

SSTL Class I

Data strobe P byte lane 0

DDR3_HPS_DQS_N3

R21

Differential 1.5-V

SSTL Class I

Data strobe N byte lane 0

DDR3_HPS_DQS_P2

R19

Differential 1.5-V

SSTL Class I

Data strobe P byte lane 1

DDR3_HPS_DQS_P3

R22

Differential 1.5-V

SSTL Class I

Data strobe N byte lane 1

Table 2–33. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 5)

Board

Reference

Schematic

Signal Name

Cyclone V SoC

Pin Number

I/O Standard Description

1 2 ... 46 47 48 49 50 51 52 53 54 55 56 ... 67 68

Komentarze do niniejszej Instrukcji

Brak uwag

Altera Cyclone V SoC Development Board Instrukcja Użytkownika Strona 51

Komentarze do niniejszej Instrukcji

Powiązane produkty i podręczniki dla Urządzenia pomiarowe Altera Cyclone V SoC Development Board