Altera Cyclone V SoC Development Board Instrukcja Użytkownika Strona 27

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Chapter 2: Board Components 2–19
Setup Elements
November 2013 Altera Corporation Cyclone V SoC Development Board
Reference Manual
HPS Jumpers
The HPS jumpers define the bootstrap options for the HPS—boot source, mode, HPS
clocks settings, POR mode and peripherals selection.
Table 211 lists the jumper settings and its descriptions.
CPU Reset Push Button
The CPU reset push button,
CPU_RESETn
(S10), is an input to the Cyclone V HPS pin
and is an open-drain I/O from the MAX V CPLD System Controller. This push button
is the default reset for both the HPS and CPLD logic. The MAX II CPLD 5M2210 also
drives this push button during power-on-reset (POR).
Table 2–11. HPS Jumpers
Board
Reference
Schematic Signal
Name
Description
J28, J29, J30
BOOTSEL[0:2]
Selects the boot mode and source for the HPS.
0x0—Reserved
0x1—FPGA (HPS-to-FPGA bridge)
0x2—1.8 V NAND flash
0x3—3.0 V NAND flash
0x4—1.8 V SD/MMC flash memory with external
transceiver
0x5—3.0 V SD/MMC flash memory with internal
transceiver
0x6—1.8 V SPI or quad SPI flash memory
0x7—3.0 V SPI or quad SPI flash memory
J26, J27
CLKSEL[0:1]
Selects the HPS clock settings. The actual clock settings are
also dependent on
BOOTSEL[0:2]
.
J13
OSC1_CLK_SEL
Selects the source of OSC1 clock.
ON: Select on-board clock generator.
OFF: Select external source via SMA connector.
J31
LTC_EXP_SPI_I2C
Selects the LTC expansion header interface type.
ON: Select SPI.
OFF: Select I
2
C.
J6
JTAG_HPS_SEL
HPS in JTAG chain or only connect HPS to MICTOR.
Selects the source to control the HPS.
ON: Select on-board USB-Blaster II as the JTAG master.
OFF: Select MICTOR-based JTAG master, such as
DSTREAM or Lauterbach programming cables. Also, sets
SW4.1 to ON to remove the on-board USB Blaster II from
driving the HPS JTAG input port in this mode.
J7
JTAG_SEL
Selects the source of the JTAG chain.
ON: Select on-board USB-Blaster II as the source.
OFF: Select MICTOR as the source.
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