Altera Cyclone V SoC Development Board Instrukcja Użytkownika Pobierz pdf (Strona 23)

Chapter 2: Board Components 2–15

FPGA Configuration

November 2013 Altera Corporation Cyclone V SoC Development Board

Reference Manual

Figure 2–4 shows the PFL configuration.

f For more information on the following topics, refer to the respective documents:

■ Board Update Portal, PFL design, and flash memory map storage, refer to the

Cyclone V SoC Development Kit User Guide

■ PFL megafunction, refer to Parallel Flash Loader Megafunction User Guide.

FPGA Programming over External USB-Blaster

The JTAG chain header provides another method for configuring the FPGA using an

external USB-Blaster device with the Quartus II Programmer running on a PC. To

prevent contention between the JTAG masters, the embedded USB-Blaster is

automatically disabled when you connect an external USB-Blaster to the JTAG chain

through the JTAG chain header.

Figure 2–4. PFL Configuration

MAX V CPLD

5M2210 System Controller

FPGA_DATA [3:0]

FPGA_DCLK

EPCQ_nCS

FLASH_A [25:1]

FLASH_D [15:0]

DATA [3:0]

DCLK

nSTATUS

nCONFIG

CONF_DONE

MSEL4

MSEL3

MSEL2

MSEL1

MSEL[4:0] and

BOOTSEL[3:0]

also connects to the

MAX V CPLD

2.5 V

10 kΩ

nCE

DATA [3:0]

DCLK

nCE

CFI Flash

FLASH_CEn

FLASH_OEn

FLASH_WEn

FLASH_A [25:0]

FLASH_D [15:0]

FLASH_CEn

FLASH_OEn

FLASH_WEn

FLASH_WPn

FLASH_ADVn

FPGA_nCONFIG

FPGA_CONF_DONE

FLASH_RYBSYn

FPGA_nSTATUS

2.5 V

10 kΩ

FLASH_ADVn

CVP_CONF_DONE

2.5 V

FLASH_CLK

FLASH_RSTn

FLASH_RESETn

FPGA_DATA [4] DATA [4]

FPGA_DATA [7:5] DATA [7:5]

PS PORT

EPCQ

56.2 Ω

100 Ω56.2 Ω

56.2 Ω

50 MHz

100 MHz

INIT_DONE

CVP_CONFDONE

FPGA_INIT_DONE

FPGA_CVP_DONE

2.5 V

2.5 V 2.5 V

MAX_ERROR

MAX_LOAD

FACTORY

USB_BLASTER

SECURITY_MODE

FACTORY_LOAD

Si570_EN

CLK125A_EN

MAX_RESETn

PGM_CONFIG

PGM_SEL

PGM_LED0

PGM_LED1

PGM_LED2

DIP Switch

BOOTSEL0

BOOTSEL1

BOOTSEL2

DIP Switch

10 kΩ

Cyclone V SoC

1 2 ... 18 19 20 21 22 23 24 25 26 27 28 ... 67 68

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