Altera Interlaken MegaCore Function Instrukcja Użytkownika Strona 23
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June 2012 Altera Corporation Interlaken MegaCore Function
User Guide
3. Parameter Settings
Customize the Interlaken MegaCore function by specifying parameters in the
Interlaken parameter editor, which you access from the MegaWizard Plug-In Manager
or from the Qsys tool in the Quartus II software.
This chapter describes the parameters and how they affect the behavior of the
MegaCore function. To customize your Interlaken MegaCore function, you can
modify parameters to specify the following properties:
■ Operational mode
■ Number of lanes
■ Lane rate
■ Meta frame length
■ Whether the MegaCore function includes or excludes the transceiver
■ Whether the MegaCore function enables out-of-band flow control
■ Number of pages of in-band flow control calendar bits
■ Whether the BurstMax and BurstShort parameters are dynamically configurable
■ BurstMax value, if not dynamically configurable
■ BurstShort value, in variations with a datapath width of 512 bits, if not
dynamically configurable
General Parameters
This section lists the basic parameters that affect the configuration of the Interlaken
MegaCore function.
Operational Mode
The Operational mode parameter specifies whether the MegaCore function is
configured to support simultaneous bidirectional communication. The operational
mode with simultaneous bidirectional communication is called duplex mode. The
current version of the MegaCore function supports only Duplex mode.
Number of Lanes
The Number of lanes parameter specifies the number of lanes available for Interlaken
communication. Supported values are 4, 8, 10, 12, and 20.
- User Guide 1
- Interlaken MegaCore Function 1
- Contents 3
- Chapter 5. Signals 4
- Contents v 5
- Features 7
- Device Family Support 8
- MegaCore Verification 9
- Release Information 10
- Installation and Licensing 10
- OpenCore Evaluation 12
- 2. Getting Started 13
- Qsys Design Flow Summary 14
- Qsys Design Flow 16
- Specifying Parameters 17
- Completing the Qsys System 18
- Simulating the System 18
- Specifying Constraints 19
- I/O Standard Constraints 20
- 3. Parameter Settings 23
- Lane Rate 24
- Number of Words in Meta Frame 24
- Exclude Transceiver 24
- Burst Parameters 25
- 4. Functional Description 27
- Architecture Overview 28
- Interfaces Overview 28
- Note to Table 4–1: 29
- Avalon-ST Interface 30
- Clocking and Reset Structure 31
- MAC Clock Verified Frequency 35
- PCS Clock Frequencies 36
- Transmit Path 37
- Receive Path 43
- Channel Filtering Blocks 45
- Packet Regrouper 45
- Calendar and Status Block 46
- Lane Status Block 47
- High-Speed I/O Block 48
- Transceivers 49
- 5. Signals 53
- Exclude transceivers 54
- Chapter 5: Signals 5–3 55
- Note to Table 5–2: 56
- Note to Table 5–3: 56
- Application Interface Signals 57
- Note to Table 5–6: 58
- Chapter 5: Signals 5–7 59
- Note to Table 5–8: 60
- Note to Table 5–9: 61
- Note to Table 5–10: 61
- Note to Table 5–11: 62
- Note to Table 5–12: 62
- Transceiver Banks 63
- Running a Design Example 65
- Setting Up the Design Example 66
- Function 69
- Simulation 73
- Reset Signals 79
- Required Reset Sequence 80
- Additional Information 87
- Typographic Conventions 88
- Visual Cue Meaning 89
- Info–4 Additional Information 90
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