Altera Interlaken MegaCore Function Instrukcja Użytkownika Strona 40
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4–14 Chapter 4: Functional Description
Transmit Path
Interlaken MegaCore Function June 2012 Altera Corporation
User Guide
MegaCore function to insert idle symbols on the Interlaken link. Figure 4–10 shows
the end of the 1016-byte packet on
tx_ch0_datain_data
, and the resulting non-zero
value of
tx_ch0_datain_empty
. This example does not illustrate use of a non-zero
empty signal partway through a packet transfer, although the arbiter does check the
empty signal on every clock cycle in which valid data is transfered.
Figure 4–8 shows the application utilizing the Interlaken link fully. The Interlaken
MegaCore function backpressures the application to prevent overflow, by deasserting
the
tx_ch0_datain_ready
signal. When it is ready to accept data again, it reasserts the
tx_ch0_datain_ready signal, and the channel can resume sending new data.
Figure 4–7. Beginning of 1016-Byte Packet Transfer on Channel 0
tx_mac_c_clk
tx_ch0_datain_ready
tx_ch0_datain_valid
tx_ch0_datain_data[127:0]
tx_ch0_datain_empty[3:0]
tx_ch0_datain_startofpacket
tx_ch0_datain_endofpacket
tx_ch0_datain_error
B0-B15
B16-B31 B32-B47 B48-B63
4h'0 4h'0 4h'0 4h'0
Figure 4–8. Full Link Utilization During 1016-Byte Packet Transfer on Channel 0
tx_mac_c_clk
tx_ch0_datain_ready
tx_ch0_datain_valid
tx_ch0_datain_data[127:0]
tx_ch0_datain_empty[3:0]
tx_ch0_datain_startofpacket
tx_ch0_datain_endofpacket
tx_ch0_datain_error
4h'0 4h'0 4h'0 4h'0 4h'0 4h'0 4h'0 4h'0
- User Guide 1
- Interlaken MegaCore Function 1
- Contents 3
- Chapter 5. Signals 4
- Contents v 5
- Features 7
- Device Family Support 8
- MegaCore Verification 9
- Release Information 10
- Installation and Licensing 10
- OpenCore Evaluation 12
- 2. Getting Started 13
- Qsys Design Flow Summary 14
- Qsys Design Flow 16
- Specifying Parameters 17
- Completing the Qsys System 18
- Simulating the System 18
- Specifying Constraints 19
- I/O Standard Constraints 20
- 3. Parameter Settings 23
- Lane Rate 24
- Number of Words in Meta Frame 24
- Exclude Transceiver 24
- Burst Parameters 25
- 4. Functional Description 27
- Architecture Overview 28
- Interfaces Overview 28
- Note to Table 4–1: 29
- Avalon-ST Interface 30
- Clocking and Reset Structure 31
- MAC Clock Verified Frequency 35
- PCS Clock Frequencies 36
- Transmit Path 37
- Receive Path 43
- Channel Filtering Blocks 45
- Packet Regrouper 45
- Calendar and Status Block 46
- Lane Status Block 47
- High-Speed I/O Block 48
- Transceivers 49
- 5. Signals 53
- Exclude transceivers 54
- Chapter 5: Signals 5–3 55
- Note to Table 5–2: 56
- Note to Table 5–3: 56
- Application Interface Signals 57
- Note to Table 5–6: 58
- Chapter 5: Signals 5–7 59
- Note to Table 5–8: 60
- Note to Table 5–9: 61
- Note to Table 5–10: 61
- Note to Table 5–11: 62
- Note to Table 5–12: 62
- Transceiver Banks 63
- Running a Design Example 65
- Setting Up the Design Example 66
- Function 69
- Simulation 73
- Reset Signals 79
- Required Reset Sequence 80
- Additional Information 87
- Typographic Conventions 88
- Visual Cue Meaning 89
- Info–4 Additional Information 90
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