Altera LVDS SERDES Instrukcja Użytkownika Pobierz pdf (Strona 3)

Figure 1: Altera LVDS SERDES Channel Diagram

DIN DOUT

DOUT DIN DOUT DIN

DOUT DIN

Clock

Multiplexer

lvds_loaden

lvds_fclk

rx_coreclock

IOPLL

8 Serial LVDS

Clock Phases

dpa_loaden

dpa_fclk

rx_divfwdclk

rx_coreclock

FPGA

Fabric

LVDS Clock Domain

DPA Clock Domain

DPA Circuitry

Retimed

Data

DIN

DPA Clock

rx_inclock/tx_inclock

tx_out

Serializer

lvds_fclk

dpa_fclk

fclk

loaden

fclk

Deserializer Bitslip

LVDS Receiver

rx_in

lvds_loaden

lvds_fclk

tx_coreclock

LVDS Transmitter

tx_in

tx_coreclock

rx_out

DPA FIFO

(Local Clock Generator)

Each Altera LVDS SERDES channel can be broken down into the following paths, with seven functional

units:

Clock DomainModesBlockPath

LVDSTX modeSerializerTX Data Path

Altera Corporation

Altera LVDS SERDES IP Core User Guide

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Functional Description

ug_altera_lvds

2014.08.18

1 2 3 4 5 6 7 8 ... 26 27

Features 1
Functional Modes 1
Functional Description 2
Clock DomainModesBlockPath 3
Serializer 4
Initialization and Reset 5
Resetting the DPA 6
Aligning the Word Boundaries 7
2014.08.18 10
Parameter Settings 11
PLL Settings Tab 12
Receiver Settings Tab 12
DescriptionValueParameter 13
Transmitter Settings Tab 15
Clock Resource Summary Tab 16
Timing Components 19
Timing Constraints and Files 19
Timing Analysis 20
Obtaining RSKM Report 22
Timing Analysis in FPGA 23
Design Example 24
References 25
Altera Corporation 26
Send Feedback 26
Document Revision History 27

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